Help, how to support cross page hardware L2 prefetch in ARM core? [ARM][Prefetcher][TLB]

[xfbingshan]

Discussed in https://github.com/orgs/gem5/discussions/1028

^{Originally posted by xfbingshan April 15, 2024}
Hi, all:
My GEM5 version is based on 21.2.
I just want to add a prefetcher in L2 Cache, while output address of the prefetcher can be cross page wildy, the defaul prefetcher configuration is not support of cross page, and the prefetching address can not send to memory.
queued.cc

for (AddrPriority& addr_prio : addresses) {

        // Block align prefetch address
        addr_prio.first = blockAddress(addr_prio.first);

        if (!samePage(addr_prio.first, pfi.getAddr())) {
            statsQueued.pfSpanPage += 1;
        }

        bool can_cross_page = (tlb != nullptr);
        if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) {
            PrefetchInfo new_pfi(pfi,addr_prio.first);
            statsQueued.pfIdentified++;
            DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
                    "inserting into prefetch queue.\n", new_pfi.getAddr());
            // Create and insert the request
            insert(pkt, new_pfi, addr_prio.second);
            num_pfs += 1;
            if (num_pfs == max_pfs) {
                break;
            }
        } else {
            DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
        }
    }

and I set some configuration to add a TLB in my own cache configuration file:

if (system.cpu[i].l2.prefetch_on_access):
    system.cpu[i].l2.prefetcher.registerTLB(system.cpu[i].mmu.l2_shared)

Unfortunately, it is not work when I found the output:

build/ARM/arch/arm/tlb.hh:287: panic: unimplemented
Memory Usage: 56109796 KBytes

Thread 1 "gem5.opt" received signal SIGABRT, Aborted.
__GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50
50      ../sysdeps/unix/sysv/linux/raise.c: No such file or directory.

and the src/arch/arm/tlb.hh code is:

void
    translateTiming(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Translation *translation,
                    BaseMMU::Mode mode) override
    {
        panic("unimplemented");
    }

My question is:

1. Why the functions of TLB such as translateTiming() are unimplemented only in arm archtecture, is there any restriction I don't know?
2. Is there any shortcuts to support wildy prefetching address to issue?