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We need to add:\n\n* Add FEATURE_CFGR and FEATURE_SCUR for MX25L12833F\n* Add FEATURE_CFGR and FEATURE_SCUR for MX25L12835F/MX25L12873F\n* Add FEATURE_SCUR for MX25L12845E/MX25L12865E\n\nBUG=b:332486637\nTEST=In a host connect to ADL-n ChromeOS via servo, with this patch,\n flashrom -p raiden_debug_spi:target=AP,custom_rst=true\n ,serial=$(dut-control -o ccd_serialname -p 9996) --wp-status\n returns correct WP status.\nTEST=without this patch, returns error with\n \"Cannot read SECURITY: unsupported by chip\"\n\nChange-Id: I001cde6816bd099317bc9c23904c5fcbe6003241\nSigned-off-by: Hsuan Ting Chen \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82605\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"flashchips: Correct feature_bits for MX25L128*"}},{"before":"8e30a6d8f7dbdbaae7c009429cd3b3456a17e38c","after":"35a2168c323a30317156eb5b5d5a56b4811dd9af","ref":"refs/heads/main","pushedAt":"2024-05-28T22:15:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"add gcc-14 -Werror=calloc-transposed-args compatibility\n\ngcc-14 added a new `-Wcalloc-transposed-args` warning. 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The first argument to calloc is documented to be\nnumber of elements in array, while the second argument is size of each\nelement, so calloc (n, sizeof (int)) is preferred over\ncalloc (sizeof (int), n).\n```\n\nLet's fix the existing occurrences.\n\nFound-by: gcc v14.1.1 20240507\nSigned-off-by: Alexander Goncharov \nChange-Id: Icb9842fbc2fa6ad4cd9dc9384c19fd3741eadb2e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/82657\nReviewed-by: Peter Marheine \nTested-by: build bot (Jenkins) \nReviewed-by: Robert Marko \nReviewed-by: Elyes Haouas \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"add gcc-14 -Werror=calloc-transposed-args compatibility"}},{"before":"2f8e64372a80115d7905e6e45194034e3082273a","after":"8e30a6d8f7dbdbaae7c009429cd3b3456a17e38c","ref":"refs/heads/main","pushedAt":"2024-05-25T08:15:09.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"Add documentation for pico-serprog\n\nThis commit adds documentation for pico-serprog by stacksmashing:\nhttps://github.com/stacksmashing/pico-serprog\nand its fork by Riku_V: https://codeberg.org/Riku_V/pico-serprog\nto the serprog overview page.\n\nChange-Id: I457dfec52f89997f64b6c276c50b329359d61b77\nSigned-off-by: Funkeleinhorn \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82229\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"Add documentation for pico-serprog"}},{"before":"a83d996f76ea6d8ad35f53ebac70c91dace24a0f","after":"2f8e64372a80115d7905e6e45194034e3082273a","ref":"refs/heads/main","pushedAt":"2024-05-24T10:15:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME\n\nBUG=none\nBRANCH=none\nTEST= Flash image using Flashrom Tool\n\nflashrom -p raiden_debug_spi -w \nflashrom -p dediprog -w \n\nAlso tested by two people on the mailing list:\nhttps://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/TCT534OIVOFZ2HHIJ4LSADQPS27ENCG2/\n\nChange-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0\nSigned-off-by: Ravi Sarawadi \nSigned-off-by: Martin Roth \nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/58025\nTested-by: build bot (Jenkins) \nReviewed-by: Peter Marheine ","shortMessageHtmlLink":"flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME"}},{"before":"85b977151b8f5717ad00b7b7204521a823ac1ad2","after":"a83d996f76ea6d8ad35f53ebac70c91dace24a0f","ref":"refs/heads/main","pushedAt":"2024-05-23T12:15:31.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for chip model GD25LF128E\n\nAdding GD25LF128E to flashchip.c\n\nGD25LF128E: 1.8V 128Mbit, QE default fixed at 1.\nDatasheet link\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00632-GD25LF128E-Rev1.3.pdf\n\nChange-Id: I71fdc7ea1aea69d14db6af3bac2da3e7bee8abbe\nSigned-off-by: Victor Lim \nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82332\nReviewed-by: Nikolai Artemiev \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"flashchips: Add support for chip model GD25LF128E"}},{"before":"643ae4d1fcb9b3bda6f35e8ff6f5b71b1104f600","after":"85b977151b8f5717ad00b7b7204521a823ac1ad2","ref":"refs/heads/main","pushedAt":"2024-05-19T10:14:45.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"ichspi.c: Add support for region 9 and beyond in Meteor Lake\n\nSince Meteor Lake, configuring region access for FREG9 and higher is\nnecessary. This configuration is determined using BIOS_BM registers:\n\nBIOS_BM_RAP (Offset 0x118): BIOS Master Read Access Permissions.\nEach bit [15:0] corresponds to a region [15:0].\nA set bit grants BIOS master read access.\n\nBIOS_BM_WAP (Offset 0x11c): BIOS Master Write Access Permissions.\nEach bit [15:0] corresponds to a region [15:0].\nA set bit grants BIOS master write/erase access.\n\nMove CHIPSET_METEOR_LAKE to the bottom of the ich_chipset list to ensure\nthat all the newer chipsets in the future will use BIOS_BM check by\ndefault.\n\nBUG=b:319773700, b:304439294\nBUG=b:319336080\nTEST=On MTL, use flashrom -VV to see correct FREG9 access\nTEST=On ADL, use flashrom -VV to see not break anything\nTEST=On APL, use flashrom -VV to see not break anything\n\nChange-Id: I1e06e7b3d470423a6014e623826d9234fdebfbf9\nSigned-off-by: Hsuan Ting Chen \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81357\nReviewed-by: Jamie Ryu \nReviewed-by: Nikolai Artemiev \nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"ichspi.c: Add support for region 9 and beyond in Meteor Lake"}},{"before":"138387aa67c6aaac8661427f4701e34d82fae48f","after":"643ae4d1fcb9b3bda6f35e8ff6f5b71b1104f600","ref":"refs/heads/main","pushedAt":"2024-05-17T08:18:10.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for MXIC MX25L3273F\n\nThe MX25L3273F has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25L3273F datasheet is available at the following URL:\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8661/MX25L3273F,%203V,%2032Mb,%20v1.2.pdf\n\nChange-Id: I4adaaa796d1db34702e7b0ed8e6fb167a3a5f6d7\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81562\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add support for MXIC MX25L3273F"}},{"before":"0f2128d74844db7cc535011a8f3ddca410ff0f5e","after":"138387aa67c6aaac8661427f4701e34d82fae48f","ref":"refs/heads/main","pushedAt":"2024-05-17T04:17:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"erasure_layout: don't copy region buffers if they're null/zero-size\n\nmemcpy() function expects 2nd parameter to be non-null. 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Print a warning instead on\nan error.\n\nBUG=b:336220545\nBRANCH=none\nTEST=build\n\nChange-Id: I14c3b55e387443909ca1efab2fc1901f87dd66d6\nSigned-off-by: Nikolai Artemiev \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82175\nReviewed-by: Hsuan-ting Chen \nReviewed-by: Brian Norris \nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashrom: Change chip unlock error to warning"}},{"before":"59c4597071cb75fa27d5db7211eb8ea095218b5f","after":"751409e6909514109383920d1c34be223e968211","ref":"refs/heads/main","pushedAt":"2024-05-09T12:16:35.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"doc: Add user doc with links to ChromeOS documents\n\nChange-Id: If7b06c077b34f73bc6c33f617332dfc32b982c12\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82181\nTested-by: build bot (Jenkins) \nReviewed-by: Hsuan-ting Chen ","shortMessageHtmlLink":"doc: Add user doc with links to ChromeOS documents"}},{"before":"5737ff972e8361b6ebf673b8954e86cb6a28da46","after":"59c4597071cb75fa27d5db7211eb8ea095218b5f","ref":"refs/heads/main","pushedAt":"2024-05-09T02:15:28.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"Make sleep threshold for delays configurable\n\nThis allows the minimum time that default_delay() will choose to sleep\nfor instead of polling to be configured at build-time. The default\nremains unchanged at 100 milliseconds for now.\n\nThe test's correctness has been checked by testing with minimum sleep\ntime left at its default and set to a non-default value smaller than 100\nmicroseconds (both pass without sleeping, verified with strace) and with\nthe minimum sleep time set to 0 (causing the test to be skipped). The\nconfigured value from the macro needs to be stored in a const to avoid\n-Werror=type-limits errors when configured to be zero.\n\nChange-Id: Ida96e0816ac914ed69d6fd82ad90ebe89cdef1cc\nSigned-off-by: Peter Marheine \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81606\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"Make sleep threshold for delays configurable"}},{"before":"e558ef1fb9c261c7a39ec50bef4f71505958dab0","after":"5737ff972e8361b6ebf673b8954e86cb6a28da46","ref":"refs/heads/main","pushedAt":"2024-05-06T10:17:48.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashrom_tester: Correct \"WP screw\" message\n\nflashrom_tester prints hints on how to modify hardware write protect\nstate as follows:\n\n...\n > connect the battery (and/or open the WP screw)\n...\n > disconnect the battery (and/or open the WP screw)\n...\n\nThe first advice should be \"[...] close the WP screw\".\n\nTEST=`flashrom_tester --flashrom_binary=$(which flashrom) \\\n internal Erase_and_Write Fail_to_verify`\n\nChange-Id: I45f06db51e92e68bf724b13bdf5b31bba511d270\nSigned-off-by: Brian Norris \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82083\nReviewed-by: Hsuan-ting Chen \nReviewed-by: Evan Benn \nReviewed-by: Anastasia Klimchuk \nReviewed-by: Angel Pons \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"flashrom_tester: Correct \"WP screw\" message"}},{"before":"c2bb2eff4c93f22266a72b0dcbfdedcc5d8a456f","after":"e558ef1fb9c261c7a39ec50bef4f71505958dab0","ref":"refs/heads/main","pushedAt":"2024-05-03T04:17:52.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for MXIC MX25L1633E\n\nThe MX25L1633E has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25L1633E datasheet is available at the following URL:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8617/MX25L1633E,%203V,%2016Mb,%20v1.8.pdf\n\nChange-Id: I63ee0182ad6e62b7408136285aa0e927d53f7bc8\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81836\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add support for MXIC MX25L1633E"}},{"before":"183208b5cb397c9b58762900502e6b1b0a358ae6","after":"c2bb2eff4c93f22266a72b0dcbfdedcc5d8a456f","ref":"refs/heads/main","pushedAt":"2024-04-29T10:16:15.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for MXIC MX25L3239E\n\nThe MX25L3239E has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25L3239E datasheet is available at the following URL:\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8613/MX25L3239E,%203V,%2032Mb,%20v1.3.pdf\n\nChange-Id: Ic7a848028fe937deb1bf83ef2a9dddf1330334b6\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81563\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add support for MXIC MX25L3239E"}},{"before":"a79ec2425e31899293b1b50d3f7ef790a207f06f","after":"183208b5cb397c9b58762900502e6b1b0a358ae6","ref":"refs/heads/main","pushedAt":"2024-04-26T00:16:09.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"udelay: only use OS time for delays, except on DOS\n\nAs proposed on the mailing list (\"RFC: remove the calibrated delay\nloop\" [1]), this removes the calibrated delay loop and uses OS-based\ntiming functions for all delays because the calibrated delay loop can\ndelay for shorter times than intended.\n\nWhen sleeping this now uses nanosleep() unconditionally, since usleep\nwas only used on DOS (where DJGPP lacks nanosleep). When busy-looping,\nit uses clock_gettime() with CLOCK_MONOTONIC or CLOCK_REALTIME depending\non availability, and gettimeofday() otherwise.\n\nThe calibrated delay loop is retained for DOS only, because timer\nresolution on DJGPP is only about 50 milliseconds. Since typical delays\nin flashrom are around 10 microseconds, using OS timing there would\nregress performance by around 500x. The old implementation is reused\nwith some branches removed based on the knowledge that timer resolution\nwill not be better than about 50 milliseconds.\n\nTested by reading and writing flash on several Intel and AMD systems:\n\n * Lenovo P920 (Intel C620, read/verify only)\n * \"nissa\" chromebook (Intel Alder Lake-N)\n * \"zork\" chromebook (AMD Zen+)\n\n[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/HFH6UHPAKA4JDL4YKPSQPO72KXSSRGME/\n\nSigned-off-by: Peter Marheine \nChange-Id: I7ac5450d194a475143698d65d64d8bcd2fd25e3f\nReviewed-on: https://review.coreboot.org/c/flashrom/+/81545\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) \nReviewed-by: Brian Norris ","shortMessageHtmlLink":"udelay: only use OS time for delays, except on DOS"}},{"before":"be95e0be1f106f717a0aadfc5bf63f310ded8435","after":"a79ec2425e31899293b1b50d3f7ef790a207f06f","ref":"refs/heads/main","pushedAt":"2024-04-22T08:16:24.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Split and add write-protect support for MX25L12833F\n\nMX25L12833F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V,%20128Mb,%20v1.0.pdf\nStatus register: page 30 table 7 (BP0~BP3, SRWD)\nConfiguration register: page 31 table 8 (TB)\nSecurity register: page 57 table 12 (WPSEL)\n\nMX25L12835F datasheet:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf\nStatus register: page 31(BP0~BP3, SRWD)\nConfiguration register: page 32 table 7 (TB)\nSecurity register: page 61 table 9 (WPSEL)\n\nMX25L12845E datasheet: (no CONFIG)\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8693/MX25L12845E,%203V,%20128Mb,%20v1.9.pdf\nStatus register: page 17 (BP0~BP3, SRWD)\nSecurity register: page 29 (WPSEL)\n\nMX25L12865E datasheet: (no CONFIG)\nhttps://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L6465E,_MX25L12865E.pdf\nStatus register: page 19 (BP0~BP3, SRWD)\nSecurity register: page 31 (WPSEL)\n\nMX25L12873F datasheet: (no hardware WP)\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8652/MX25L12873F,%203V,%20128Mb,%20v1.2.pdf\nStatus register: page 31(BP0~BP3, SRWD)\nConfiguration register: page 32 table 7 (TB)\nSecurity register: page 60 table 9 (WPSEL)\n\nSplits the MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F\ngroup into three subgroups:\n* MX25L12833F: This chip have the configuration register and WP tested\n* MX25L12835F/MX25L12873F: These chips have the configuration register.\n* MX25L12845E/MX25L12865E: These chips don't have the configuration\n register.\n\nTests the write protect functionality on the MX25L12833F chip only.\n\nBUG=b:332486637\nTEST=Test flashrom --wp-disable with MX25L12833FZNI-10 on ChromeOS\n\nChange-Id: I379c833eea3ed3487504126f45c6df672a772ddc\nSigned-off-by: Hsuan Ting Chen \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81792\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Split and add write-protect support for MX25L12833F"}},{"before":"85f14efe065504a81dc803ad34bdaa669176d3eb","after":"be95e0be1f106f717a0aadfc5bf63f310ded8435","ref":"refs/heads/main","pushedAt":"2024-04-22T06:15:48.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add write protect function support for MX25R1635F\n\nThe MX25R1635F has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25R1635F datasheet is available at the following URL:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8702/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf\n\nChange-Id: I6e2b417ab177039618069d8e35132ddbfb814f03\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81840\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add write protect function support for MX25R1635F"}},{"before":"e5ed0c6340961594dcf1a22f9907d91d576b4885","after":"85f14efe065504a81dc803ad34bdaa669176d3eb","ref":"refs/heads/main","pushedAt":"2024-04-21T10:16:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"ich: Add names for region 5, 9, 10, 11, 12, 15\n\nAdd Region 9 for Intel Meteor Lake; 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