[VCU118][build_bitstream] [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0

[nguyensinhton]

Background Work

• Yes, I searched the mailing list
• Yes, I searched prior issues
• Yes, I searched the documentation

FireSim Version and Hash

1.17.0

OS Setup

Ubuntu 20.04

Other Setup

No response

Current Behavior

I am following this guide to build a bitstream for VCU118:
https://docs.fires.im/en/more-vcu118-fix/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-VCU118.html

During the process, I encountered the following error: 'A LUT2 cell in the design is missing a connection on input pin I0.'
Detail :
<<>>
Starting Connectivity Check Task

Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 5740.148 ; gain = 0.000 ; free physical = 2299 ; free virtual = 21887
INFO: [Common 17-83] Releasing license: Implementation
31 Infos, 100 Warnings, 4 Critical Warnings and 1 Errors encountered.
opt_design failed
ERROR: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: partition_wrapper/partition/dwidth_adapt_64bits_512bits_1/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_pktfifo_r_upsizer.pktfifo_read_data_inst/dw_fifogen_ar_i_21.
Resolution: Please review the preceding OPT INFO messages that detail what has been trimmed in the design to determine if the removal of unused logic is causing this error. If opt_design is being specified directly, it will need to be rerun with opt_design -verbose to generate detailed INFO messages about trimming.
INFO: [Common 17-206] Exiting Vivado at Wed Jul 19 16:31:38 2023...
FireSim Xilinx Alveo xilinx_vcu118 FPGA Build Failed
Your FPGA build failed for quintuplet: xilinx_vcu118-firesim-FireSim-FireSimRocket4GiBDRAMConfig-BaseXilinxVCU118Config
ERROR: A bitstream build failed.
Fatal error.
<<<>>>

This seems to be a standard error, and I found a related article on the Xilinx support website: https://support.xilinx.com/s/article/70111?language=en_US

However, I'm having trouble resolving this error. I tried using the 'set dont touch' attribute, but it was not successful.
Can anyone provide guidance on how to resolve this issue?

Thank you !

Expected Behavior

generate bitstream successfully

Other Information

No response