Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[VCU118][build_bitstream] Starting Connectivity Check Task during build bitsteam got FAIL #1611

Open
3 tasks done
nguyensinhton opened this issue Jul 19, 2023 · 0 comments
Open
3 tasks done
Labels
bug Something isn't working

Comments

@nguyensinhton
Copy link

Background Work

FireSim Version and Hash

1.17.0

OS Setup

ubuntu 20.04 LTS

Other Setup

Current Behavior

I follow this guide to build bitstream for VCU118:

https://docs.fires.im/en/more-vcu118-fix/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-VCU118.html

i got a specific ERROR related to Connectivity Check Task;
the error as below:

`
Starting Connectivity Check Task

Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 5740.148 ; gain = 0.000 ; free physical = 2299 ; free virtual = 21887
INFO: [Common 17-83] Releasing license: Implementation
31 Infos, 100 Warnings, 4 Critical Warnings and 1 Errors encountered.
opt_design failed
ERROR: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: partition_wrapper/partition/dwidth_adapt_64bits_512bits_1/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_pktfifo_r_upsizer.pktfifo_read_data_inst/dw_fifogen_ar_i_21.
Resolution: Please review the preceding OPT INFO messages that detail what has been trimmed in the design to determine if the removal of unused logic is causing this error. If opt_design is being specified directly, it will need to be rerun with opt_design -verbose to generate detailed INFO messages about trimming.
INFO: [Common 17-206] Exiting Vivado at Wed Jul 19 16:31:38 2023...
FireSim Xilinx Alveo xilinx_vcu118 FPGA Build Failed
Your FPGA build failed for quintuplet: xilinx_vcu118-firesim-FireSim-FireSimRocket4GiBDRAMConfig-BaseXilinxVCU118Config
ERROR: A bitstream build failed.
Fatal error.
`

Could you help me resolve it ?
Thank you

Expected Behavior

build bit steam successfully

Other Information

No response

@nguyensinhton nguyensinhton added the bug Something isn't working label Jul 19, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
bug Something isn't working
Projects
None yet
Development

No branches or pull requests

1 participant