We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
1.16.0-464-g0e412143e
<!-- copy/paste the output of `uname -a; lsb_release -a` below -->
Linux a7 4.15.0-200-generic #211-Ubuntu SMP Thu Nov 24 18:16:04 UTC 2022 x86_64 GNU/Linux LSB Version: core-9.20170808ubuntu1-noarch:security-9.20170808ubuntu1-noarch Distributor ID: Ubuntu Description: Ubuntu 18.04.6 LTS Release: 18.04 Codename: bionic
Fresh Chipyard repo , with fresh Conda environment.
It builds dromajo .a file in the right Conda env but then searches for it in base
The two should match
2023-06-13 20:50:16,486 [main ] [INFO ] FireSim Manager. Docs: https://docs.fires.im Running: infrasetup 2023-06-13 20:50:16,492 [__init__ ] [WARNI] xilinx_u250_firesim_rocket_split_soc is overriding a deploy quintuplet in your config_hwdb.yaml file. Make sure you understand why! 2023-06-13 20:50:16,492 [__init__ ] [DEBUG] RuntimeHWConfig self.platform None 2023-06-13 20:50:16,492 [__init__ ] [WARNI] xilinx_u250_firesim_rocket_split_tile is overriding a deploy quintuplet in your config_hwdb.yaml file. Make sure you understand why! 2023-06-13 20:50:16,492 [__init__ ] [DEBUG] RuntimeHWConfig self.platform None 2023-06-13 20:50:16,492 [__init__ ] [DEBUG] {'config_file_name': 'config_hwdb.yaml', 'hwconf_dict': {'xilinx_u250_firesim_rocket_split_soc': <runtools.runtime_config.RuntimeHWConfig object at 0x7f83cc039ff0>, 'xilinx_u250_firesim_rocket_split_tile': <runtools.runtime_config.RuntimeHWConfig object at 0x7f83cc039c90>}, 'simulation_mode_string': 'FPGA simulation'} 2023-06-13 20:50:16,530 [__init__ ] [DEBUG] {'autocounter_config': AutoCounterConfig(readrate=0), 'default_plusarg_passthrough': '', 'defaulthwconfig': 'firesim_rocket_quadcore_no_nic_l2_llc4mb_ddr3', 'hostdebug_config': HostDebugConfig(zero_out_dram=False, disable_synth_asserts=False), 'linklatency': 3, 'metasimulation_enabled': True, 'metasimulation_host_simulator': 'verilator-debug', 'metasimulation_only_plusargs': '+fesvr-step-size=128 +max-cycles=100000000', 'metasimulation_only_vcs_plusargs': '+vcs+initreg+0 +vcs+initmem+0', 'netbandwidth': 200, 'no_net_num_nodes': 2, 'partition_config': PartitionConfig(batch_size=28), 'profileinterval': -1, 'run_farm_dispatcher': <runtools.run_farm.ExternallyProvisioned object at 0x7f83cc039c30>, 'suffixtag': None, 'switchinglatency': 0, 'synthprint_config': SynthPrintConfig(start=0, end=-1, cycle_prefix=True), 'terminateoncompletion': False, 'topology': 'fireaxe_xilinx_u250_split_rocket_tile_from_soc_config', 'tracerv_config': TracerVConfig(enable=True, select=0, start=0, end=-1, output_format=0), 'workload_name': 'hello.json'} 2023-06-13 20:50:16,551 [__init__ ] [DEBUG] {'config_file_name': 'config_build_recipes.yaml', 'hwconf_dict': {'xilinx_u250_firesim_rocket_split_soc': <runtools.runtime_config.RuntimeBuildRecipeConfig object at 0x7f83cc03a710>, 'xilinx_u250_firesim_rocket_split_tile': <runtools.runtime_config.RuntimeBuildRecipeConfig object at 0x7f83cc039930>}, 'simulation_mode_string': 'Metasimulation'} 2023-06-13 20:50:16,551 [flush ] [DEBUG] defaultpartitionconfig PartitionConfig(batch_size=28) 2023-06-13 20:50:16,551 [allocate_sim] [INFO ] run_farm_hosts_dict defaultdict(<class 'list'>, {'localhost': [(<runtools.run_farm.Inst object at 0x7f83cc039bd0>, None)]}) 2023-06-13 20:50:16,551 [pass_simple_] [INFO ] add_pipe <runtools.firesim_topology_elements.FireSimPipeNode object at 0x7f83cc039db0> 0 2023-06-13 20:50:16,551 [pass_simple_] [INFO ] add_simulation <runtools.firesim_topology_elements.FireSimServerNode object at 0x7f83cc039a50> 0 2023-06-13 20:50:16,551 [pass_simple_] [INFO ] add_simulation <runtools.firesim_topology_elements.FireSimServerNode object at 0x7f83cc03a5f0> 1 2023-06-13 20:50:16,552 [pass_apply_d] [DEBUG] pass_apply_default_hwconfig, RuntimeHWConfig: xilinx_u250_firesim_rocket_split_soc DeployQuintuplet: xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile AGFI: None Bitstream tar: None CustomRuntimeConf: None 2023-06-13 20:50:16,552 [set_server_h] [INFO ] set_server_hardware_config 0 xilinx_u250_firesim_rocket_split_soc 2023-06-13 20:50:16,552 [pass_apply_d] [DEBUG] pass_apply_default_hwconfig, RuntimeHWConfig: xilinx_u250_firesim_rocket_split_tile DeployQuintuplet: xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitInner-RocketTile AGFI: None Bitstream tar: None CustomRuntimeConf: None 2023-06-13 20:50:16,552 [set_server_h] [INFO ] set_server_hardware_config 1 xilinx_u250_firesim_rocket_split_tile 2023-06-13 20:50:16,556 [decorator ] [DEBUG] deprecate positional args: graphviz.backend.piping.pipe(['renderer', 'formatter', 'neato_no_op', 'quiet']) 2023-06-13 20:50:16,557 [decorator ] [DEBUG] deprecate positional args: graphviz.backend.rendering.render(['renderer', 'formatter', 'neato_no_op', 'quiet']) 2023-06-13 20:50:16,557 [decorator ] [DEBUG] deprecate positional args: graphviz.backend.unflattening.unflatten(['stagger', 'fanout', 'chain', 'encoding']) 2023-06-13 20:50:16,558 [decorator ] [DEBUG] deprecate positional args: graphviz.backend.viewing.view(['quiet']) 2023-06-13 20:50:16,560 [decorator ] [DEBUG] deprecate positional args: graphviz.quoting.quote(['is_html_string', 'is_valid_id', 'dot_keywords', 'endswith_odd_number_of_backslashes', 'escape_unescaped_quotes']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.quoting.a_list(['kwargs', 'attributes']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.quoting.attr_list(['kwargs', 'attributes']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.dot.Dot.clear(['keep_attrs']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.dot.Dot.__iter__(['subgraph']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.dot.Dot.node(['_attributes']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.dot.Dot.edge(['_attributes']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.dot.Dot.attr(['_attributes']) 2023-06-13 20:50:16,561 [decorator ] [DEBUG] deprecate positional args: graphviz.dot.Dot.subgraph(['name', 'comment', 'graph_attr', 'node_attr', 'edge_attr', 'body']) 2023-06-13 20:50:16,562 [decorator ] [DEBUG] deprecate positional args: graphviz.piping.Pipe._pipe_legacy(['renderer', 'formatter', 'neato_no_op', 'quiet']) 2023-06-13 20:50:16,563 [decorator ] [DEBUG] deprecate positional args: graphviz.saving.Save.save(['directory']) 2023-06-13 20:50:16,563 [decorator ] [DEBUG] deprecate positional args: graphviz.rendering.Render.render(['directory', 'view', 'cleanup', 'format', 'renderer', 'formatter', 'neato_no_op', 'quiet', 'quiet_view']) 2023-06-13 20:50:16,563 [decorator ] [DEBUG] deprecate positional args: graphviz.rendering.Render.view(['directory', 'cleanup', 'quiet', 'quiet_view']) 2023-06-13 20:50:16,564 [decorator ] [DEBUG] deprecate positional args: graphviz.unflattening.Unflatten.unflatten(['stagger', 'fanout', 'chain']) 2023-06-13 20:50:16,564 [decorator ] [DEBUG] deprecate positional args: graphviz.graphs.BaseGraph.__init__(['comment', 'filename', 'directory', 'format', 'engine', 'encoding', 'graph_attr', 'node_attr', 'edge_attr', 'body', 'strict']) 2023-06-13 20:50:16,565 [decorator ] [DEBUG] deprecate positional args: graphviz.sources.Source.from_file(['directory', 'format', 'engine', 'encoding', 'renderer', 'formatter']) 2023-06-13 20:50:16,565 [decorator ] [DEBUG] deprecate positional args: graphviz.sources.Source.__init__(['filename', 'directory', 'format', 'engine', 'encoding']) 2023-06-13 20:50:16,565 [decorator ] [DEBUG] deprecate positional args: graphviz.sources.Source.save(['directory']) 2023-06-13 20:50:16,566 [mkdirs ] [DEBUG] os.makedirs('generated-topology-diagrams') 2023-06-13 20:50:16,566 [save ] [DEBUG] write lines to 'generated-topology-diagrams/firesim_topologyfireaxe_xilinx_u250_split_rocket_tile_from_soc_config.gv' 2023-06-13 20:50:16,566 [run_check ] [DEBUG] run [PosixPath('dot'), '-Kdot', '-Tpdf', '-O', 'firesim_topologyfireaxe_xilinx_u250_split_rocket_tile_from_soc_config.gv'] 2023-06-13 20:50:16,603 [flush ] [DEBUG] [localhost] Executing task 'instance_liveness' 2023-06-13 20:50:16,608 [instance_liv] [INFO ] [localhost] Checking if host instance is up... 2023-06-13 20:50:16,609 [flush ] [DEBUG] [localhost] run: uname -a 2023-06-13 20:50:17,379 [flush ] [DEBUG] [localhost] out: /home/eecs/iansseijelly/.bashrc: line 33: /opt/xilinx/xrt/setup.sh: No such file or directory 2023-06-13 20:50:17,624 [flush ] [DEBUG] [localhost] out: /home/eecs/iansseijelly/.bashrc: line 33: /opt/xilinx/xrt/setup.sh: No such file or directory 2023-06-13 20:50:17,844 [flush ] [DEBUG] [localhost] out: Linux a7 4.15.0-200-generic #211-Ubuntu SMP Thu Nov 24 18:16:04 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux 2023-06-13 20:50:17,844 [flush ] [DEBUG] [localhost] out: 2023-06-13 20:50:17,847 [flush ] [DEBUG] [localhost] run: echo $SHELL 2023-06-13 20:50:17,897 [flush ] [DEBUG] [localhost] out: /home/eecs/iansseijelly/.bashrc: line 33: /opt/xilinx/xrt/setup.sh: No such file or directory 2023-06-13 20:50:18,153 [flush ] [DEBUG] [localhost] out: /home/eecs/iansseijelly/.bashrc: line 33: /opt/xilinx/xrt/setup.sh: No such file or directory 2023-06-13 20:50:18,360 [flush ] [DEBUG] [localhost] out: /bin/bash 2023-06-13 20:50:18,361 [flush ] [DEBUG] [localhost] out: 2023-06-13 20:50:18,385 [flush ] [DEBUG] [localhost] Executing task 'build_drivers_helper' 2023-06-13 20:50:18,385 [get_deployqu] [DEBUG] get_deployquintuplet_for_config xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile <bound method RuntimeHWConfig.get_platform of <runtools.runtime_config.RuntimeBuildRecipeConfig object at 0x7f83cc03a710>> 2023-06-13 20:50:18,385 [get_deployqu] [DEBUG] get_deployquintuplet_for_config xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile <bound method RuntimeHWConfig.get_platform of <runtools.runtime_config.RuntimeBuildRecipeConfig object at 0x7f83cc03a710>> 2023-06-13 20:50:18,385 [build_sim_dr] [INFO ] Building Metasim driver for xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile 2023-06-13 20:50:18,386 [flush ] [INFO ] [localhost] local: pwd 2023-06-13 20:50:18,387 [flush ] [INFO ] [localhost] run: make PLATFORM=xilinx_alveo_u250 TARGET_PROJECT=firesim DESIGN=FireSim TARGET_CONFIG=WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig PLATFORM_CONFIG=BaseXilinxAlveoConfig TARGET_SPLIT_MODE=SplitOuter TARGET_SPLIT_MODULE=RocketTile verilator-debug 2023-06-13 20:50:19,172 [flush ] [INFO ] [localhost] out: /home/eecs/iansseijelly/.bashrc: line 33: /opt/xilinx/xrt/setup.sh: No such file or directory 2023-06-13 20:50:19,397 [flush ] [INFO ] [localhost] out: /home/eecs/iansseijelly/.bashrc: line 33: /opt/xilinx/xrt/setup.sh: No such file or directory 2023-06-13 20:50:19,630 [flush ] [INFO ] [localhost] out: Running with RISCV=/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/riscv-tools 2023-06-13 20:50:20,208 [flush ] [INFO ] [localhost] out: make -C /scratch/iansseijelly/multi-fpga-chipyard/tools/dromajo/dromajo-src/src 2023-06-13 20:50:20,211 [flush ] [INFO ] [localhost] out: make[1]: Entering directory '/scratch/iansseijelly/multi-fpga-chipyard/tools/dromajo/dromajo-src/src' 2023-06-13 20:50:20,216 [flush ] [INFO ] [localhost] out: make[1]: Nothing to be done for 'all'. 2023-06-13 20:50:20,216 [flush ] [INFO ] [localhost] out: make[1]: Leaving directory '/scratch/iansseijelly/multi-fpga-chipyard/tools/dromajo/dromajo-src/src' 2023-06-13 20:50:20,229 [flush ] [INFO ] [localhost] out: make -C /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/midas/src/main/cc -j8 VM_PARALLEL_BUILDS=1 verilator-debug PLATFORM=xilinx_alveo_u250 DRIVER_NAME=FireSim GEN_FILE_BASENAME=FireSim-generated GEN_DIR=/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile DRIVER="/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/src/main/cc/firesim/firesim_top.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/blockdev.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/dromajo.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/groundtest.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/simplenic.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/tracerv.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/tsibridge.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/uart.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/fesvr/firesim_tsi.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/tracerv/tracerv_dwarf.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/tracerv/tracerv_elf.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/tracerv/tracerv_processing.cc /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/firesim-lib/src/main/cc/bridges/tracerv/trace_tracker.cc /scratch/iansseijelly/multi-fpga-chipyard/.conda-env/riscv-tools/lib/libfesvr.a /scratch/iansseijelly/conda-install/lib/libdromajo_cosim.a /scratch/iansseijelly/multi-fpga-chipyard/generators/testchipip/src/main/resources/testchipip/csrc/testchip_tsi.cc" TOP_DIR=/scratch/iansseijelly/multi-fpga-chipyard VERILATOR_FLAGS="--assert" 2023-06-13 20:50:20,241 [flush ] [INFO ] [localhost] out: make[1]: Entering directory '/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/midas/src/main/cc' 2023-06-13 20:50:20,242 [flush ] [INFO ] [localhost] out: make[1]: *** No rule to make target '/scratch/iansseijelly/conda-install/lib/libdromajo_cosim.a', needed by '/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile/VFireSim-debug'. Stop. 2023-06-13 20:50:20,242 [flush ] [INFO ] [localhost] out: make[1]: Leaving directory '/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/midas/src/main/cc' 2023-06-13 20:50:20,242 [flush ] [INFO ] [localhost] out: make: *** [make/verilator.mk:33: /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig-BaseXilinxAlveoConfig-SplitOuter-RocketTile/VFireSim-debug] Error 2 2023-06-13 20:50:20,243 [flush ] [INFO ] [localhost] out: 2023-06-13 20:50:20,244 [flush ] [INFO ] Fatal error: run() received nonzero return code 2 while executing! 2023-06-13 20:50:20,244 [flush ] [INFO ] Requested: make PLATFORM=xilinx_alveo_u250 TARGET_PROJECT=firesim DESIGN=FireSim TARGET_CONFIG=WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig PLATFORM_CONFIG=BaseXilinxAlveoConfig TARGET_SPLIT_MODE=SplitOuter TARGET_SPLIT_MODULE=RocketTile verilator-debug 2023-06-13 20:50:20,245 [flush ] [INFO ] Executed: /bin/bash -l -c "cd /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/../ && export RISCV=/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/riscv-tools && export PATH=/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/utils/fireperf:/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/utils/fireperf/FlameGraph:/scratch/iansseijelly/multi-fpga-chipyard/software/firemarshal:/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/riscv-tools/bin:/ecad/tools/xilinx/Vitis_HLS/2021.1/bin:/ecad/tools/xilinx/Model_Composer/2021.1/bin:/ecad/tools/xilinx/Vitis/2021.1/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/microblaze/lin/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/arm/lin/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch64/lin/aarch64-linux/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch64/lin/aarch64-none/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/ecad/tools/xilinx/Vitis/2021.1/tps/lnx64/cmake-3.3.2/bin:/ecad/tools/xilinx/Vitis/2021.1/aietools/bin:/ecad/tools/xilinx/Vivado/2021.1/bin:/ecad/tools/xilinx/DocNav:/home/eecs/iansseijelly/.vscode-server/bin/b380da4ef1ee00e224a15c1d4d9793e27c2b6302/bin/remote-cli:/ecad/tools/xilinx/Vitis_HLS/2021.1/bin:/ecad/tools/xilinx/Model_Composer/2021.1/bin:/ecad/tools/xilinx/Vitis/2021.1/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/microblaze/lin/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/arm/lin/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch64/lin/aarch64-linux/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch64/lin/aarch64-none/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/ecad/tools/xilinx/Vitis/2021.1/tps/lnx64/cmake-3.3.2/bin:/ecad/tools/xilinx/Vitis/2021.1/aietools/bin:/ecad/tools/xilinx/Vivado/2021.1/bin:/ecad/tools/xilinx/DocNav:/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/bin:/scratch/iansseijelly/conda-install/condabin:/ecad/tools/xilinx/Vitis_HLS/2021.1/bin:/ecad/tools/xilinx/Model_Composer/2021.1/bin:/ecad/tools/xilinx/Vitis/2021.1/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/microblaze/lin/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/arm/lin/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch64/lin/aarch64-linux/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/aarch64/lin/aarch64-none/bin:/ecad/tools/xilinx/Vitis/2021.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/ecad/tools/xilinx/Vitis/2021.1/tps/lnx64/cmake-3.3.2/bin:/ecad/tools/xilinx/Vitis/2021.1/aietools/bin:/ecad/tools/xilinx/Vivado/2021.1/bin:/ecad/tools/xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/usr/local/bin:/ecad/tools/scripts:/ecad/tools/synopsys/installer/current:/ecad/tools/synopsys/vcs/current/bin:/ecad/tools/synopsys/syn/current/bin:/ecad/tools/synopsys/icc/current/bin:/ecad/tools/synopsys/mw/current/bin/AMD.64:/ecad/tools/synopsys/starrc/current/bin:/ecad/tools/synopsys/rail/current/bin/IA.32:/ecad/tools/synopsys/pts/current/bin:/ecad/tools/synopsys/astro/current/bin/IA.32:/ecad/tools/synopsys/cadabra/current/bin:/ecad/tools/synopsys/fm/current/bin:/ecad/tools/mentor/calibre/current/bin:/ecad/tools/synopsys/verdi/current/bin:/ecad/tools/cadence/XCELIUM/current/tools/bin/64bit:/ecad/tools/cadence/XCELIUM/current/tools/bin:/usr/local/bin:/ecad/tools/scripts:/ecad/tools/synopsys/installer/current:/ecad/tools/synopsys/vcs/current/bin:/ecad/tools/synopsys/syn/current/bin:/ecad/tools/synopsys/icc/current/bin:/ecad/tools/synopsys/mw/current/bin/AMD.64:/ecad/tools/synopsys/starrc/current/bin:/ecad/tools/synopsys/rail/current/bin/IA.32:/ecad/tools/synopsys/pts/current/bin:/ecad/tools/synopsys/astro/current/bin/IA.32:/ecad/tools/synopsys/cadabra/current/bin:/ecad/tools/synopsys/fm/current/bin:/ecad/tools/mentor/calibre/current/bin:/ecad/tools/synopsys/verdi/current/bin:/ecad/tools/cadence/XCELIUM/current/tools/bin/64bit:/ecad/tools/cadence/XCELIUM/current/tools/bin:/ecad/tools/scripts:/ecad/tools/synopsys/installer/current:/ecad/tools/synopsys/vcs/current/bin:/ecad/tools/synopsys/syn/current/bin:/ecad/tools/synopsys/icc/current/bin:/ecad/tools/synopsys/mw/current/bin/AMD.64:/ecad/tools/synopsys/starrc/current/bin:/ecad/tools/synopsys/rail/current/bin/IA.32:/ecad/tools/synopsys/pts/current/bin:/ecad/tools/synopsys/astro/current/bin/IA.32:/ecad/tools/synopsys/cadabra/current/bin:/ecad/tools/synopsys/fm/current/bin:/ecad/tools/mentor/calibre/current/bin:/ecad/tools/synopsys/verdi/current/bin:/ecad/tools/cadence/XCELIUM/current/tools/bin/64bit:/ecad/tools/cadence/XCELIUM/current/tools/bin:/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy && export LD_LIBRARY_PATH=/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/riscv-tools/lib:/scratch/iansseijelly/local-lib:/scratch/iansseijelly/local-lib:/scratch/iansseijelly/local-lib && source sourceme-manager.sh --skip-ssh-setup && cd sim/ && make PLATFORM=xilinx_alveo_u250 TARGET_PROJECT=firesim DESIGN=FireSim TARGET_CONFIG=WithDefaultFireSimBridges_WithNoTraceFireSimConfigTweaks_chipyard.RocketConfig PLATFORM_CONFIG=BaseXilinxAlveoConfig TARGET_SPLIT_MODE=SplitOuter TARGET_SPLIT_MODULE=RocketTile verilator-debug" 2023-06-13 20:50:20,245 [flush ] [INFO ] Aborting. 2023-06-13 20:50:20,245 [<module> ] [ERROR] Fatal error. Traceback (most recent call last): File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/firesim", line 515, in <module> main(args) File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/firesim", line 454, in main t['task'](t['config'](args)) File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/firesim", line 228, in infrasetup runtime_conf.infrasetup() File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/runtools/runtime_config.py", line 916, in infrasetup self.firesim_topology_with_passes.infrasetup_passes(use_mock_instances_for_testing) File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/runtools/firesim_topology_with_passes.py", line 481, in infrasetup_passes self.pass_build_required_drivers() File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/runtools/firesim_topology_with_passes.py", line 439, in pass_build_required_drivers execute(build_drivers_helper, servers, hosts=['localhost']) File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/tasks.py", line 356, in execute results[host] = _execute( File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/tasks.py", line 247, in _execute return task.run(*args, **kwargs) File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/tasks.py", line 147, in run return self.wrapped(*args, **kwargs) File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/runtools/firesim_topology_with_passes.py", line 435, in build_drivers_helper resolved_cfg.build_sim_driver() File "/scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/runtools/runtime_config.py", line 516, in build_sim_driver buildresult = run(driverbuildcommand) File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/network.py", line 688, in host_prompting_wrapper return func(*args, **kwargs) File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/operations.py", line 1068, in run return _run_command( File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/operations.py", line 944, in _run_command error(message=msg, stdout=out, stderr=err) File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/utils.py", line 357, in error return func(message) File "/scratch/iansseijelly/multi-fpga-chipyard/.conda-env/lib/python3.10/site-packages/fabric/utils.py", line 65, in abort raise e SystemExit: 1 2023-06-13 20:50:20,247 [<module> ] [INFO ] The full log of this run is: /scratch/iansseijelly/multi-fpga-chipyard/sims/firesim/deploy/logs/2023-06-14--03-50-16-infrasetup-EQVXX87B3MM3DCIM.log
The text was updated successfully, but these errors were encountered:
joonho3020
No branches or pull requests
Background Work
FireSim Version and Hash
1.16.0-464-g0e412143e
OS Setup
Linux a7 4.15.0-200-generic #211-Ubuntu SMP Thu Nov 24 18:16:04 UTC 2022 x86_64 GNU/Linux
LSB Version: core-9.20170808ubuntu1-noarch:security-9.20170808ubuntu1-noarch
Distributor ID: Ubuntu
Description: Ubuntu 18.04.6 LTS
Release: 18.04
Codename: bionic
Other Setup
Fresh Chipyard repo , with fresh Conda environment.
Current Behavior
It builds dromajo .a file in the right Conda env but then searches for it in base
Expected Behavior
The two should match
Other Information
The text was updated successfully, but these errors were encountered: