/
hwintrinsicarm64.cpp
1889 lines (1562 loc) · 65.4 KB
/
hwintrinsicarm64.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "jitpch.h"
#include "hwintrinsic.h"
#ifdef FEATURE_HW_INTRINSICS
//------------------------------------------------------------------------
// Arm64VersionOfIsa: Gets the corresponding 64-bit only InstructionSet for a given InstructionSet
//
// Arguments:
// isa -- The InstructionSet ID
//
// Return Value:
// The 64-bit only InstructionSet associated with isa
static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa)
{
switch (isa)
{
case InstructionSet_AdvSimd:
return InstructionSet_AdvSimd_Arm64;
case InstructionSet_Aes:
return InstructionSet_Aes_Arm64;
case InstructionSet_ArmBase:
return InstructionSet_ArmBase_Arm64;
case InstructionSet_Crc32:
return InstructionSet_Crc32_Arm64;
case InstructionSet_Dp:
return InstructionSet_Dp_Arm64;
case InstructionSet_Sha1:
return InstructionSet_Sha1_Arm64;
case InstructionSet_Sha256:
return InstructionSet_Sha256_Arm64;
case InstructionSet_Rdm:
return InstructionSet_Rdm_Arm64;
default:
return InstructionSet_NONE;
}
}
//------------------------------------------------------------------------
// lookupInstructionSet: Gets the InstructionSet for a given class name
//
// Arguments:
// className -- The name of the class associated with the InstructionSet to lookup
//
// Return Value:
// The InstructionSet associated with className
static CORINFO_InstructionSet lookupInstructionSet(const char* className)
{
assert(className != nullptr);
if (className[0] == 'A')
{
if (strcmp(className, "AdvSimd") == 0)
{
return InstructionSet_AdvSimd;
}
if (strcmp(className, "Aes") == 0)
{
return InstructionSet_Aes;
}
if (strcmp(className, "ArmBase") == 0)
{
return InstructionSet_ArmBase;
}
}
else if (className[0] == 'C')
{
if (strcmp(className, "Crc32") == 0)
{
return InstructionSet_Crc32;
}
}
else if (className[0] == 'D')
{
if (strcmp(className, "Dp") == 0)
{
return InstructionSet_Dp;
}
}
else if (className[0] == 'R')
{
if (strcmp(className, "Rdm") == 0)
{
return InstructionSet_Rdm;
}
}
else if (className[0] == 'S')
{
if (strcmp(className, "Sha1") == 0)
{
return InstructionSet_Sha1;
}
if (strcmp(className, "Sha256") == 0)
{
return InstructionSet_Sha256;
}
}
else if (className[0] == 'V')
{
if (strncmp(className, "Vector64", 8) == 0)
{
return InstructionSet_Vector64;
}
else if (strncmp(className, "Vector128", 9) == 0)
{
return InstructionSet_Vector128;
}
}
return InstructionSet_ILLEGAL;
}
//------------------------------------------------------------------------
// lookupIsa: Gets the InstructionSet for a given class name and enclsoing class name
//
// Arguments:
// className -- The name of the class associated with the InstructionSet to lookup
// enclosingClassName -- The name of the enclosing class or nullptr if one doesn't exist
//
// Return Value:
// The InstructionSet associated with className and enclosingClassName
CORINFO_InstructionSet HWIntrinsicInfo::lookupIsa(const char* className, const char* enclosingClassName)
{
assert(className != nullptr);
if (strcmp(className, "Arm64") == 0)
{
assert(enclosingClassName != nullptr);
return Arm64VersionOfIsa(lookupInstructionSet(enclosingClassName));
}
else
{
return lookupInstructionSet(className);
}
}
//------------------------------------------------------------------------
// isFullyImplementedIsa: Gets a value that indicates whether the InstructionSet is fully implemented
//
// Arguments:
// isa - The InstructionSet to check
//
// Return Value:
// true if isa is supported; otherwise, false
bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa)
{
switch (isa)
{
// These ISAs are fully implemented
case InstructionSet_AdvSimd:
case InstructionSet_AdvSimd_Arm64:
case InstructionSet_Aes:
case InstructionSet_Aes_Arm64:
case InstructionSet_ArmBase:
case InstructionSet_ArmBase_Arm64:
case InstructionSet_Crc32:
case InstructionSet_Crc32_Arm64:
case InstructionSet_Dp:
case InstructionSet_Dp_Arm64:
case InstructionSet_Rdm:
case InstructionSet_Rdm_Arm64:
case InstructionSet_Sha1:
case InstructionSet_Sha1_Arm64:
case InstructionSet_Sha256:
case InstructionSet_Sha256_Arm64:
case InstructionSet_Vector64:
case InstructionSet_Vector128:
return true;
default:
return false;
}
}
//------------------------------------------------------------------------
// isScalarIsa: Gets a value that indicates whether the InstructionSet is scalar
//
// Arguments:
// isa - The InstructionSet to check
//
// Return Value:
// true if isa is scalar; otherwise, false
bool HWIntrinsicInfo::isScalarIsa(CORINFO_InstructionSet isa)
{
switch (isa)
{
case InstructionSet_ArmBase:
case InstructionSet_ArmBase_Arm64:
case InstructionSet_Crc32:
case InstructionSet_Crc32_Arm64:
{
return true;
}
default:
{
return false;
}
}
}
//------------------------------------------------------------------------
// lookupImmBounds: Gets the lower and upper bounds for the imm-value of a given NamedIntrinsic
//
// Arguments:
// intrinsic -- NamedIntrinsic associated with the HWIntrinsic to lookup
// simdType -- vector size
// baseType -- base type of the Vector64/128<T>
// pImmLowerBound [OUT] - The lower incl. bound for a value of the intrinsic immediate operand
// pImmUpperBound [OUT] - The upper incl. bound for a value of the intrinsic immediate operand
//
void HWIntrinsicInfo::lookupImmBounds(
NamedIntrinsic intrinsic, int simdSize, var_types baseType, int* pImmLowerBound, int* pImmUpperBound)
{
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
bool hasImmediateOperand = HasImmediateOperand(intrinsic);
assert(hasImmediateOperand);
assert(pImmLowerBound != nullptr);
assert(pImmUpperBound != nullptr);
int immLowerBound = 0;
int immUpperBound = 0;
if (category == HW_Category_ShiftLeftByImmediate)
{
// The left shift amount is in the range 0 to the element width in bits minus 1.
immUpperBound = BITS_PER_BYTE * genTypeSize(baseType) - 1;
}
else if (category == HW_Category_ShiftRightByImmediate)
{
// The right shift amount, in the range 1 to the element width in bits.
immLowerBound = 1;
immUpperBound = BITS_PER_BYTE * genTypeSize(baseType);
}
else if (category == HW_Category_SIMDByIndexedElement)
{
immUpperBound = Compiler::getSIMDVectorLength(simdSize, baseType) - 1;
}
else
{
switch (intrinsic)
{
case NI_AdvSimd_DuplicateSelectedScalarToVector64:
case NI_AdvSimd_DuplicateSelectedScalarToVector128:
case NI_AdvSimd_Extract:
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_ExtractVector64:
case NI_AdvSimd_Insert:
case NI_AdvSimd_InsertScalar:
case NI_AdvSimd_LoadAndInsertScalar:
case NI_AdvSimd_StoreSelectedScalar:
case NI_AdvSimd_Arm64_DuplicateSelectedScalarToVector128:
case NI_AdvSimd_Arm64_InsertSelectedScalar:
immUpperBound = Compiler::getSIMDVectorLength(simdSize, baseType) - 1;
break;
default:
unreached();
}
}
assert(immLowerBound <= immUpperBound);
*pImmLowerBound = immLowerBound;
*pImmUpperBound = immUpperBound;
}
//------------------------------------------------------------------------
// impNonConstFallback: generate alternate code when the imm-arg is not a compile-time constant
//
// Arguments:
// intrinsic -- intrinsic ID
// simdType -- Vector type
// simdBaseJitType -- base JIT type of the Vector64/128<T>
//
// Return Value:
// return the IR of semantic alternative on non-const imm-arg
//
GenTree* Compiler::impNonConstFallback(NamedIntrinsic intrinsic, var_types simdType, CorInfoType simdBaseJitType)
{
return nullptr;
}
//------------------------------------------------------------------------
// impSpecialIntrinsic: Import a hardware intrinsic that requires special handling as a GT_HWINTRINSIC node if possible
//
// Arguments:
// intrinsic -- id of the intrinsic function.
// clsHnd -- class handle containing the intrinsic function.
// method -- method handle of the intrinsic function.
// sig -- signature of the intrinsic call.
// simdBaseJitType -- generic argument of the intrinsic.
// retType -- return type of the intrinsic.
//
// Return Value:
// The GT_HWINTRINSIC node, or nullptr if not a supported intrinsic
//
GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_CLASS_HANDLE clsHnd,
CORINFO_METHOD_HANDLE method,
CORINFO_SIG_INFO* sig,
CorInfoType simdBaseJitType,
var_types retType,
unsigned simdSize)
{
const HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
const int numArgs = sig->numArgs;
// The vast majority of "special" intrinsics are Vector64/Vector128 methods.
// The only exception is ArmBase.Yield which should be treated differently.
if (intrinsic == NI_ArmBase_Yield)
{
assert(sig->numArgs == 0);
assert(JITtype2varType(sig->retType) == TYP_VOID);
assert(simdSize == 0);
return gtNewScalarHWIntrinsicNode(TYP_VOID, intrinsic);
}
assert(category != HW_Category_Scalar);
assert(!HWIntrinsicInfo::isScalarIsa(HWIntrinsicInfo::lookupIsa(intrinsic)));
assert(numArgs >= 0);
var_types simdBaseType = JitType2PreciseVarType(simdBaseJitType);
assert(varTypeIsArithmetic(simdBaseType));
GenTree* retNode = nullptr;
GenTree* op1 = nullptr;
GenTree* op2 = nullptr;
GenTree* op3 = nullptr;
GenTree* op4 = nullptr;
switch (intrinsic)
{
case NI_Vector64_Abs:
case NI_Vector128_Abs:
{
assert(sig->numArgs == 1);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdAbsNode(retType, op1, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_Add:
case NI_Vector128_Add:
case NI_Vector64_op_Addition:
case NI_Vector128_op_Addition:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack(retType);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdBinOpNode(GT_ADD, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_AndNot:
case NI_Vector128_AndNot:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack(retType);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdBinOpNode(GT_AND_NOT, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_As:
case NI_Vector64_AsByte:
case NI_Vector64_AsDouble:
case NI_Vector64_AsInt16:
case NI_Vector64_AsInt32:
case NI_Vector64_AsInt64:
case NI_Vector64_AsNInt:
case NI_Vector64_AsNUInt:
case NI_Vector64_AsSByte:
case NI_Vector64_AsSingle:
case NI_Vector64_AsUInt16:
case NI_Vector64_AsUInt32:
case NI_Vector64_AsUInt64:
case NI_Vector128_As:
case NI_Vector128_AsByte:
case NI_Vector128_AsDouble:
case NI_Vector128_AsInt16:
case NI_Vector128_AsInt32:
case NI_Vector128_AsInt64:
case NI_Vector128_AsNInt:
case NI_Vector128_AsNUInt:
case NI_Vector128_AsSByte:
case NI_Vector128_AsSingle:
case NI_Vector128_AsUInt16:
case NI_Vector128_AsUInt32:
case NI_Vector128_AsUInt64:
case NI_Vector128_AsVector:
case NI_Vector128_AsVector4:
{
assert(!sig->hasThis());
assert(numArgs == 1);
// We fold away the cast here, as it only exists to satisfy
// the type system. It is safe to do this here since the retNode type
// and the signature return type are both the same TYP_SIMD.
retNode = impSIMDPopStack(retType, /* expectAddr: */ false, sig->retTypeClass);
SetOpLclRelatedToSIMDIntrinsic(retNode);
assert(retNode->gtType == getSIMDTypeForSize(getSIMDTypeSizeInBytes(sig->retTypeSigClass)));
break;
}
case NI_Vector128_AsVector2:
{
assert(sig->numArgs == 1);
assert((simdSize == 16) && (simdBaseType == TYP_FLOAT));
assert(retType == TYP_SIMD8);
op1 = impSIMDPopStack(TYP_SIMD16);
retNode = gtNewSimdHWIntrinsicNode(TYP_SIMD8, op1, NI_Vector128_GetLower, simdBaseJitType, simdSize);
break;
}
case NI_Vector128_AsVector3:
{
assert(sig->numArgs == 1);
assert((simdSize == 16) && (simdBaseType == TYP_FLOAT));
assert(retType == TYP_SIMD12);
op1 = impSIMDPopStack(TYP_SIMD16);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, simdBaseJitType, simdSize);
break;
}
case NI_Vector128_AsVector128:
{
assert(!sig->hasThis());
assert(numArgs == 1);
assert(retType == TYP_SIMD16);
switch (getSIMDTypeForSize(simdSize))
{
case TYP_SIMD8:
{
assert((simdSize == 8) && (simdBaseType == TYP_FLOAT));
op1 = impSIMDPopStack(TYP_SIMD8);
if (op1->IsCnsVec())
{
GenTreeVecCon* vecCon = op1->AsVecCon();
vecCon->gtType = TYP_SIMD16;
vecCon->gtSimdVal.f32[2] = 0.0f;
vecCon->gtSimdVal.f32[3] = 0.0f;
return vecCon;
}
GenTree* idx = gtNewIconNode(2, TYP_INT);
GenTree* zero = gtNewZeroConNode(TYP_FLOAT);
op1 = gtNewSimdWithElementNode(retType, op1, idx, zero, simdBaseJitType, 16,
/* isSimdAsHWIntrinsic */ false);
idx = gtNewIconNode(3, TYP_INT);
zero = gtNewZeroConNode(TYP_FLOAT);
retNode = gtNewSimdWithElementNode(retType, op1, idx, zero, simdBaseJitType, 16,
/* isSimdAsHWIntrinsic */ false);
break;
}
case TYP_SIMD12:
{
assert((simdSize == 12) && (simdBaseType == TYP_FLOAT));
op1 = impSIMDPopStack(TYP_SIMD12);
if (op1->IsCnsVec())
{
GenTreeVecCon* vecCon = op1->AsVecCon();
vecCon->gtType = TYP_SIMD16;
vecCon->gtSimdVal.f32[3] = 0.0f;
return vecCon;
}
GenTree* idx = gtNewIconNode(3, TYP_INT);
GenTree* zero = gtNewZeroConNode(TYP_FLOAT);
retNode = gtNewSimdWithElementNode(retType, op1, idx, zero, simdBaseJitType, 16,
/* isSimdAsHWIntrinsic */ false);
break;
}
case TYP_SIMD16:
{
// We fold away the cast here, as it only exists to satisfy
// the type system. It is safe to do this here since the retNode type
// and the signature return type are both the same TYP_SIMD.
retNode = impSIMDPopStack(retType, /* expectAddr: */ false, sig->retTypeClass);
SetOpLclRelatedToSIMDIntrinsic(retNode);
assert(retNode->gtType == getSIMDTypeForSize(getSIMDTypeSizeInBytes(sig->retTypeSigClass)));
break;
}
default:
{
unreached();
}
}
break;
}
case NI_Vector64_BitwiseAnd:
case NI_Vector128_BitwiseAnd:
case NI_Vector64_op_BitwiseAnd:
case NI_Vector128_op_BitwiseAnd:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack(retType);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdBinOpNode(GT_AND, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_BitwiseOr:
case NI_Vector128_BitwiseOr:
case NI_Vector64_op_BitwiseOr:
case NI_Vector128_op_BitwiseOr:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack(retType);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdBinOpNode(GT_OR, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_Ceiling:
case NI_Vector128_Ceiling:
{
assert(sig->numArgs == 1);
assert(varTypeIsFloating(simdBaseType));
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdCeilNode(retType, op1, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_ConditionalSelect:
case NI_Vector128_ConditionalSelect:
{
assert(sig->numArgs == 3);
op3 = impSIMDPopStack(retType);
op2 = impSIMDPopStack(retType);
op1 = impSIMDPopStack(retType);
retNode =
gtNewSimdCndSelNode(retType, op1, op2, op3, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_ConvertToDouble:
case NI_Vector128_ConvertToDouble:
{
assert(sig->numArgs == 1);
assert((simdBaseType == TYP_LONG) || (simdBaseType == TYP_ULONG));
intrinsic = (simdSize == 8) ? NI_AdvSimd_Arm64_ConvertToDoubleScalar : NI_AdvSimd_Arm64_ConvertToDouble;
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToInt32:
case NI_Vector128_ConvertToInt32:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
op1 = impSIMDPopStack(retType);
retNode =
gtNewSimdHWIntrinsicNode(retType, op1, NI_AdvSimd_ConvertToInt32RoundToZero, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToInt64:
case NI_Vector128_ConvertToInt64:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
intrinsic = (simdSize == 8) ? NI_AdvSimd_Arm64_ConvertToInt64RoundToZeroScalar
: NI_AdvSimd_Arm64_ConvertToInt64RoundToZero;
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToSingle:
case NI_Vector128_ConvertToSingle:
{
assert(sig->numArgs == 1);
assert((simdBaseType == TYP_INT) || (simdBaseType == TYP_UINT));
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, NI_AdvSimd_ConvertToSingle, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToUInt32:
case NI_Vector128_ConvertToUInt32:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, NI_AdvSimd_ConvertToUInt32RoundToZero, simdBaseJitType,
simdSize);
break;
}
case NI_Vector64_ConvertToUInt64:
case NI_Vector128_ConvertToUInt64:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
intrinsic = (simdSize == 8) ? NI_AdvSimd_Arm64_ConvertToUInt64RoundToZeroScalar
: NI_AdvSimd_Arm64_ConvertToUInt64RoundToZero;
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_Create:
case NI_Vector128_Create:
{
if (sig->numArgs == 1)
{
op1 = impPopStack().val;
retNode = gtNewSimdCreateBroadcastNode(retType, op1, simdBaseJitType, simdSize);
break;
}
uint32_t simdLength = getSIMDVectorLength(simdSize, simdBaseType);
assert(sig->numArgs == simdLength);
bool isConstant = true;
if (varTypeIsFloating(simdBaseType))
{
for (uint32_t index = 0; index < sig->numArgs; index++)
{
GenTree* arg = impStackTop(index).val;
if (!arg->IsCnsFltOrDbl())
{
isConstant = false;
break;
}
}
}
else
{
assert(varTypeIsIntegral(simdBaseType));
for (uint32_t index = 0; index < sig->numArgs; index++)
{
GenTree* arg = impStackTop(index).val;
if (!arg->IsIntegralConst())
{
isConstant = false;
break;
}
}
}
if (isConstant)
{
// Some of the below code assumes 8 or 16 byte SIMD types
assert((simdSize == 8) || (simdSize == 16));
GenTreeVecCon* vecCon = gtNewVconNode(retType);
switch (simdBaseType)
{
case TYP_BYTE:
case TYP_UBYTE:
{
uint8_t cnsVal = 0;
for (uint32_t index = 0; index < sig->numArgs; index++)
{
cnsVal = static_cast<uint8_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
vecCon->gtSimdVal.u8[simdLength - 1 - index] = cnsVal;
}
break;
}
case TYP_SHORT:
case TYP_USHORT:
{
uint16_t cnsVal = 0;
for (uint32_t index = 0; index < sig->numArgs; index++)
{
cnsVal = static_cast<uint16_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
vecCon->gtSimdVal.u16[simdLength - 1 - index] = cnsVal;
}
break;
}
case TYP_INT:
case TYP_UINT:
{
uint32_t cnsVal = 0;
for (uint32_t index = 0; index < sig->numArgs; index++)
{
cnsVal = static_cast<uint32_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
vecCon->gtSimdVal.u32[simdLength - 1 - index] = cnsVal;
}
break;
}
case TYP_LONG:
case TYP_ULONG:
{
uint64_t cnsVal = 0;
for (uint32_t index = 0; index < sig->numArgs; index++)
{
cnsVal = static_cast<uint64_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
vecCon->gtSimdVal.u64[simdLength - 1 - index] = cnsVal;
}
break;
}
case TYP_FLOAT:
{
float cnsVal = 0;
for (uint32_t index = 0; index < sig->numArgs; index++)
{
cnsVal = static_cast<float>(impPopStack().val->AsDblCon()->DconValue());
vecCon->gtSimdVal.f32[simdLength - 1 - index] = cnsVal;
}
break;
}
case TYP_DOUBLE:
{
double cnsVal = 0;
for (uint32_t index = 0; index < sig->numArgs; index++)
{
cnsVal = static_cast<double>(impPopStack().val->AsDblCon()->DconValue());
vecCon->gtSimdVal.f64[simdLength - 1 - index] = cnsVal;
}
break;
}
default:
{
unreached();
}
}
retNode = vecCon;
break;
}
IntrinsicNodeBuilder nodeBuilder(getAllocator(CMK_ASTNode), sig->numArgs);
// TODO-CQ: We don't handle contiguous args for anything except TYP_FLOAT today
GenTree* prevArg = nullptr;
bool areArgsContiguous = (simdBaseType == TYP_FLOAT);
for (int i = sig->numArgs - 1; i >= 0; i--)
{
GenTree* arg = impPopStack().val;
if (areArgsContiguous)
{
if (prevArg != nullptr)
{
// Recall that we are popping the args off the stack in reverse order.
areArgsContiguous = areArgumentsContiguous(arg, prevArg);
}
prevArg = arg;
}
nodeBuilder.AddOperand(i, arg);
}
if (areArgsContiguous)
{
op1 = nodeBuilder.GetOperand(0);
GenTree* op1Address = CreateAddressNodeForSimdHWIntrinsicCreate(op1, simdBaseType, simdSize);
retNode = gtNewOperNode(GT_IND, retType, op1Address);
}
else
{
retNode =
gtNewSimdHWIntrinsicNode(retType, std::move(nodeBuilder), intrinsic, simdBaseJitType, simdSize);
}
break;
}
case NI_Vector64_CreateScalar:
case NI_Vector128_CreateScalar:
{
assert(sig->numArgs == 1);
op1 = impPopStack().val;
retNode = gtNewSimdCreateScalarNode(retType, op1, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_CreateScalarUnsafe:
case NI_Vector128_CreateScalarUnsafe:
{
assert(sig->numArgs == 1);
op1 = impPopStack().val;
retNode = gtNewSimdCreateScalarUnsafeNode(retType, op1, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_Divide:
case NI_Vector128_Divide:
case NI_Vector64_op_Division:
case NI_Vector128_op_Division:
{
assert(sig->numArgs == 2);
if (!varTypeIsFloating(simdBaseType))
{
// We can't trivially handle division for integral types using SIMD
break;
}
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
var_types argType = TYP_UNKNOWN;
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = getArgForHWIntrinsic(argType, argClass);
retNode = gtNewSimdBinOpNode(GT_DIV, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_Dot:
case NI_Vector128_Dot:
{
assert(sig->numArgs == 2);
if (!varTypeIsLong(simdBaseType))
{
var_types simdType = getSIMDTypeForSize(simdSize);
op2 = impSIMDPopStack(simdType);
op1 = impSIMDPopStack(simdType);
retNode = gtNewSimdDotProdNode(retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
}
break;
}
case NI_Vector64_Equals:
case NI_Vector128_Equals:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack(retType);
op1 = impSIMDPopStack(retType);
retNode = gtNewSimdCmpOpNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_EqualsAll:
case NI_Vector128_EqualsAll:
case NI_Vector64_op_Equality:
case NI_Vector128_op_Equality:
{
assert(sig->numArgs == 2);
var_types simdType = getSIMDTypeForSize(simdSize);
op2 = impSIMDPopStack(simdType);
op1 = impSIMDPopStack(simdType);
retNode = gtNewSimdCmpOpAllNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_EqualsAny:
case NI_Vector128_EqualsAny:
{
assert(sig->numArgs == 2);
var_types simdType = getSIMDTypeForSize(simdSize);
op2 = impSIMDPopStack(simdType);
op1 = impSIMDPopStack(simdType);
retNode = gtNewSimdCmpOpAnyNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
/* isSimdAsHWIntrinsic */ false);
break;
}
case NI_Vector64_ExtractMostSignificantBits:
case NI_Vector128_ExtractMostSignificantBits:
{
assert(sig->numArgs == 1);
// ARM64 doesn't have a single instruction that performs the behavior so we'll emulate it instead.
// To do this, we effectively perform the following steps:
// 1. tmp = input & 0x80 ; and the input to clear all but the most significant bit
// 2. tmp = tmp >> index ; right shift each element by its index
// 3. tmp = sum(tmp) ; sum the elements together
// For byte/sbyte, we also need to handle the fact that we can only shift by up to 8
// but for Vector128, we have 16 elements to handle. In that scenario, we will simply
// extract both scalars, and combine them via: (upper << 8) | lower
var_types simdType = getSIMDTypeForSize(simdSize);
op1 = impSIMDPopStack(simdType);
GenTreeVecCon* vecCon2 = gtNewVconNode(simdType);
GenTreeVecCon* vecCon3 = gtNewVconNode(simdType);
switch (simdBaseType)
{
case TYP_BYTE:
case TYP_UBYTE:
{
simdBaseType = TYP_UBYTE;
simdBaseJitType = CORINFO_TYPE_UBYTE;
vecCon2->gtSimdVal.u64[0] = 0x8080808080808080;
vecCon3->gtSimdVal.u64[0] = 0x00FFFEFDFCFBFAF9;
if (simdSize == 16)
{
vecCon2->gtSimdVal.u64[1] = 0x8080808080808080;
vecCon3->gtSimdVal.u64[1] = 0x00FFFEFDFCFBFAF9;
}
break;
}
case TYP_SHORT:
case TYP_USHORT:
{
simdBaseType = TYP_USHORT;
simdBaseJitType = CORINFO_TYPE_USHORT;
vecCon2->gtSimdVal.u64[0] = 0x8000800080008000;
vecCon3->gtSimdVal.u64[0] = 0xFFF4FFF3FFF2FFF1;
if (simdSize == 16)
{
vecCon2->gtSimdVal.u64[1] = 0x8000800080008000;
vecCon3->gtSimdVal.u64[1] = 0xFFF8FFF7FFF6FFF5;
}
break;
}
case TYP_INT: