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project_xilinx HardWare on U200 get a poor performance #177

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zyt1024 opened this issue Apr 10, 2023 · 0 comments
Open

project_xilinx HardWare on U200 get a poor performance #177

zyt1024 opened this issue Apr 10, 2023 · 0 comments

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@zyt1024
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zyt1024 commented Apr 10, 2023

Hello,I tried project_xilinx on U200, but when running VGG16 with batch_size=1 on hardware, it took 23 seconds.why it runs so slowly on U200? Please help me.
image.
this is my config file.

kernel_frequency=0:300

[connectivity]
#sp=<compute_unit_name>.<interface_name>:<sptag[min:max]>
#sp=DataLoad_1.A_in:HBM[0]
#sp=DataLoad_1.C_in:HBM[2]
#sp=DataStore_1.B_out:HBM[1]
#sp=DataStore_1.D_out:HBM[3]

#stream_connect=<cu_name>.<output_port>:<cu_name>.<input_port>:[<fifo_depth>]
stream_connect=memRead_1.bias_out:coreConv_1.bias_in
stream_connect=memRead_1.weight_out:coreConv_1.weight_in
stream_connect=memRead_1.data_out:coreConv_1.data_in
##VGG connection
stream_connect=coreConv_1.conv_out:memWrite_1.conv_in
##ResNet connection
#stream_connect=coreConv_1.conv_out:batchNorm_1.conv_in
#stream_connect=coreConv_1.bypass_out:memWrite_1.bypass_in
#stream_connect=batchNorm_1.bn_out:memWrite_1.bn_in


##used for pipelined pooling
#stream_connect=memWrite_1.pool_sync_out:maxPool_1.pool_sync_in

#nk=<kernal_name>:#:<cu_name1>.<cu_name2>...<cu_name#>
#nk=DataLoad:1:DataLoad_1
#nk=DataStore:1:DataStore_1

[vivado]
##dump all waveforms
prop=fileset.sim_1.xsim.elaborate.debug_level=all
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