Abstract Reset in Uninstantiated Module Crashes without DCE

[seldridge]

If you compile the following circuit with -X mverilog (which will disable DCE), you get a match error inside the Verilog emitter:

circuit Foo :
  module Bar :
    input a: Reset
  module Foo :
    input a: UInt<1>

# firrtl -i Tmp.fir -X mverilog
Exception in thread "main" firrtl.FirrtlInternalException: Internal Error! trying to write unsupported type in the Verilog Emitter: ResetType
Please file an issue at https://github.com/ucb-bar/firrtl/issues
        at firrtl.Utils$.error(Utils.scala:503)
        at firrtl.Utils$.throwInternalError(Utils.scala:175)
        at firrtl.VerilogEmitter.stringify(VerilogEmitter.scala:128)
        at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_ports$4(VerilogEmitter.scala:982)
        at scala.collection.immutable.List.map(List.scala:246)
        at scala.collection.immutable.List.map(List.scala:79)
        at firrtl.VerilogEmitter$VerilogRender.build_ports(VerilogEmitter.scala:981)
        at firrtl.VerilogEmitter$VerilogRender.emit_verilog(VerilogEmitter.scala:1314)
        at firrtl.VerilogEmitter.$anonfun$emit$2(VerilogEmitter.scala:1357)
        at scala.collection.immutable.List.foreach(List.scala:333)
        at firrtl.VerilogEmitter.emit(VerilogEmitter.scala:1351)
        at firrtl.VerilogEmitter.$anonfun$execute$2(VerilogEmitter.scala:1369)
        at scala.collection.immutable.List.flatMap(List.scala:293)
        at scala.collection.immutable.List.flatMap(List.scala:79)
        at firrtl.VerilogEmitter.execute(VerilogEmitter.scala:1366)
        at firrtl.Transform.transform(Compiler.scala:296)
        at firrtl.Transform.transform$(Compiler.scala:296)
        at firrtl.SeqTransform.transform(Compiler.scala:378)
        at firrtl.stage.transforms.ExpandPrepares.execute(ExpandPrepares.scala:19)
        at firrtl.Transform.transform(Compiler.scala:296)
        at firrtl.Transform.transform$(Compiler.scala:296)
        at firrtl.stage.transforms.ExpandPrepares.transform(ExpandPrepares.scala:7)
        at firrtl.stage.transforms.CatchCustomTransformExceptions.execute(CatchCustomTransformExceptions.scala:10)
        at firrtl.Transform.transform(Compiler.scala:296)
        at firrtl.Transform.transform$(Compiler.scala:296)
        at firrtl.stage.transforms.CatchCustomTransformExceptions.transform(CatchCustomTransformExceptions.scala:7)
        at firrtl.stage.transforms.UpdateAnnotations.internalTransform(UpdateAnnotations.scala:22)
        at firrtl.stage.transforms.UpdateAnnotations.internalTransform(UpdateAnnotations.scala:8)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.stage.transforms.UpdateAnnotations.transform(UpdateAnnotations.scala:8)
        at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
        at firrtl.Utils$.time(Utils.scala:181)
        at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
        at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
        at firrtl.stage.TransformManager.transform(TransformManager.scala:14)
        at firrtl.stage.phases.Compiler.$anonfun$internalTransform$6(Compiler.scala:138)
        at firrtl.Utils$.time(Utils.scala:181)
        at firrtl.stage.phases.Compiler.f$1(Compiler.scala:138)
        at firrtl.stage.phases.Compiler.$anonfun$internalTransform$8(Compiler.scala:143)
        at scala.collection.immutable.List.map(List.scala:246)
        at scala.collection.immutable.List.map(List.scala:79)
        at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:143)
        at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:53)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.stage.phases.Compiler.transform(Compiler.scala:53)
        at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:30)
        at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:17)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
        at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
        at firrtl.Utils$.time(Utils.scala:181)
        at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
        at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
        at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
        at firrtl.stage.FirrtlStage.run(FirrtlStage.scala:38)
        at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
        at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
        at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
        at logger.Logger$.$anonfun$makeScope$2(Logger.scala:167)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
        at logger.Logger$.makeScope(Logger.scala:165)
        at firrtl.options.Stage.transform(Stage.scala:47)
        at firrtl.options.Stage.execute(Stage.scala:58)
        at firrtl.options.StageMain.main(Stage.scala:71)
        at firrtl.stage.FirrtlMain.main(FirrtlStage.scala)
        at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
        at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
        at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
        at java.base/java.lang.reflect.Method.invoke(Method.java:566)
        at coursier.bootstrap.launcher.a.a(Unknown Source)
        at coursier.bootstrap.launcher.Launcher.main(Unknown Source)

I think the correct behavior here would be to add a check to high form that will check all roots in the design (and not just the main module) for any abstract resets and error if it sees any.

The above circuit will get through just fine with -X verilog because the uninstantiated module, Bar, will not have a reset inferred, but will then be DCE'd away.