Not generate waveform when using vcs to test Hello World.

[zhangkanqi]

ENV:
vcs version: VCS-MX2018.09-SP2
riscv64-unknown-elf-* version: 9.2.0

PROBLEM:
I added VCS_DEBUG into Makefile when buildng vcs:

But when execute command make vcs debug=1, it didn't generate waveform. The details are as follows:

zhangkanqi@hwfuzz:~/Cores-VeeR-EH1/tools$ make vcs debug=1
BUILD_PATH=snapshots/default /home/zhangkanqi/Cores-VeeR-EH1/configs/veer.config -target=default -set iccm_enable
veer: Set(s) requested : iccm_enable
veer: Overriding iccm_enable value 0 with 1
VeeR configuration for target=default
veer: icache_enable = 1
veer: icache_tag_low = 6
veer: icache_size = 16
veer: nmi_vec = 0x11110000
veer: external_mem_hole = default disabled
veer: lsu_stbuf_depth = 8
veer: dma_buf_depth = 4
veer: dec_instbuf_depth = 4
veer: fpga_optimize = 1
veer: lsu_num_nbload = 8
veer: sb_bus_tag = 1
veer: ifu_bus_tag = 3
veer: dma_bus_tag = 1
veer: dccm_region = 0xf
veer: dccm_num_banks = 8
veer: dccm_size = 64
veer: dccm_offset = 0x40000
veer: dccm_enable = 1
veer: reset_vec = 0x80000000
veer: ret_stack_size = 4
veer: pic_meigwctrl_count = 8
veer: pic_mpiccfg_count = 1
veer: pic_meigwclr_count = 8
veer: pic_meipt_count = 8
veer: pic_mpiccfg_offset = 0x3000
veer: pic_meigwclr_mask = 0x0
veer: pic_meipl_mask = 0xf
veer: pic_region = 0xf
veer: pic_meie_count = 8
veer: pic_meip_count = 4
veer: pic_meipl_offset = 0x0000
veer: pic_offset = 0xc0000
veer: pic_meigwctrl_offset = 0x4000
veer: pic_size = 32
veer: pic_total_int = 8
veer: pic_meigwctrl_mask = 0x3
veer: pic_meipt_offset = 0x3004
veer: pic_meie_offset = 0x2000
veer: pic_meigwclr_offset = 0x5000
veer: pic_meip_mask = 0x0
veer: pic_meipl_count = 8
veer: pic_mpiccfg_mask = 0x1
veer: pic_meip_offset = 0x1000
veer: pic_meie_mask = 0x1
veer: pic_meipt_mask = 0x0
veer: iccm_size = 512
veer: iccm_num_banks = 8
veer: iccm_region = 0xe
veer: iccm_enable = 1
veer: iccm_offset = 0xe000000
veer: btb_addr_lo = 4
veer: btb_size = 32
veer: btb_index1_lo = 4
veer: bht_addr_lo = 4
veer: bht_size = 128
veer: Writing snapshots/default/common_defines.vh
veer: Writing snapshots/default/defines.h
veer: Writing snapshots/default/pd_defines.vh
veer: Writing snapshots/default/whisper.json
veer: Writing snapshots/default/perl_configs.pl
veer: Writing snapshots/default/link.ld
riscv64-unknown-elf-cpp -Isnapshots/default /home/zhangkanqi/Cores-VeeR-EH1/testbench/tests/hello_world/hello_world.s > hello_world.cpp.s
riscv64-unknown-elf-as -mabi=ilp32 -march=rv32imc hello_world.cpp.s -o hello_world.o
Building hello_world
riscv64-unknown-elf-gcc -mabi=ilp32 -march=rv32imc -Wl,-Map=hello_world.map -lgcc -T/home/zhangkanqi/Cores-VeeR-EH1/testbench/link.ld -o hello_world.exe hello_world.o -nostartfiles
riscv64-unknown-elf-objcopy -O verilog hello_world.exe program.hex
riscv64-unknown-elf-objdump -S hello_world.exe > hello_world.dis
Completed building hello_world
vcs -full64 -debug_access -assert svaext -sverilog +error+500
+incdir+/home/zhangkanqi/Cores-VeeR-EH1/design/lib
+incdir+/home/zhangkanqi/Cores-VeeR-EH1/design/include
+incdir+snapshots/default +libext+.v
snapshots/default/common_defines.vh /home/zhangkanqi/Cores-VeeR-EH1/design/include/veer_types.sv -f /home/zhangkanqi/Cores-VeeR-EH1/testbench/flist
/home/zhangkanqi/Cores-VeeR-EH1/testbench/tb_top.sv /home/zhangkanqi/Cores-VeeR-EH1/testbench/ahb_sif.sv
-l vcs_compile.log
Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '5.15.0-89-generic' is not supported.
Supported versions are 2.4* or 2.6*.
Chronologic VCS (TM)
Version O-2018.09-SP2_Full64 -- Sun Dec 10 17:21:28 2023
Copyright (c) 1991-2018 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'snapshots/default/common_defines.vh'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/veer_types.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/veer_wrapper.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/build.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/veer_wrapper.sv'.
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/veer_wrapper.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/mem.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/mem.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/pic_ctrl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/pic_ctrl.sv'.
Parsing included file 'snapshots/default/pic_map_auto.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/pic_ctrl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/veer.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/veer.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dma_ctrl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/dma_ctrl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_aln_ctl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_aln_ctl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_compress_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_ifc_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_bp_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_ic_mem.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_ic_mem.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_mem_ctl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_mem_ctl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_iccm_mem.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu_iccm_mem.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/ifu/ifu.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec_decode_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec_gpr_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec_ib_ctl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec_ib_ctl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec_tlu_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec_trigger.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dec/dec.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/exu/exu_alu_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/exu/exu_mul_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/exu/exu_div_ctl.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/exu/exu.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_clkdomain.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_addrcheck.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_addrcheck.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_lsc_ctl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_lsc_ctl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_stbuf.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_stbuf.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_bus_buffer.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_bus_buffer.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_bus_intf.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_bus_intf.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_ecc.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_ecc.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_dccm_mem.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_dccm_mem.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_dccm_ctl.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_dccm_ctl.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/lsu/lsu_trigger.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dbg/dbg.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/design/include/global.h'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/design/dbg/dbg.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dmi/dmi_wrapper.v'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dmi/dmi_jtag_to_core_sync.v'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/design/dmi/rvjtag_tap.sv'
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/testbench/tb_top.sv'
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/testbench/dasm.svi'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/testbench/tb_top.sv'.
Parsing included file '/home/zhangkanqi/Cores-VeeR-EH1/testbench/axi_lsu_dma_bridge.sv'.
Back to file '/home/zhangkanqi/Cores-VeeR-EH1/testbench/tb_top.sv'.
Parsing design file '/home/zhangkanqi/Cores-VeeR-EH1/testbench/ahb_sif.sv'
Parsing library file '/home/zhangkanqi/Cores-VeeR-EH1/design/lib/beh_lib.sv'
Parsing library file '/home/zhangkanqi/Cores-VeeR-EH1/design/lib/mem_lib.sv'
Top Level Modules:
tb_top
No TimeScale specified
Starting vcs inline pass...
51 modules and 0 UDP read.
recompiling package veer_types
recompiling module mem
recompiling module pic_ctrl
recompiling module cmp_and_mux
recompiling module configurable_gw
recompiling module dma_ctrl
recompiling module ifu_aln_ctl
recompiling module ifu_compress_ctl
recompiling module ifu_ifc_ctl
recompiling module ifu_bp_ctl
recompiling module dec_dec_ctl
recompiling module dec_tlu_ctl
recompiling module dec_timer_ctl
recompiling module dec
recompiling module exu_alu_ctl
recompiling module exu_div_ctl
recompiling module exu
recompiling module lsu
recompiling module lsu_clkdomain
recompiling module lsu_lsc_ctl
recompiling module lsu_bus_intf
recompiling module lsu_ecc
recompiling module lsu_dccm_ctl
recompiling module lsu_trigger
recompiling module dmi_wrapper
recompiling module tb_top
recompiling module axi_lsu_dma_bridge
recompiling module axi_slv
recompiling module rvdff
recompiling module rvdffs
recompiling module rvdffsc
recompiling module rvdff_fpga
recompiling module rvdffs_fpga
recompiling module rvdffsc_fpga
recompiling module rvoclkhdr
recompiling module rvdffe
recompiling module rvsyncss
recompiling module rvbradder
recompiling module rvtwoscomp
recompiling module rvmaskandmatch
recompiling module rvbtb_tag_hash
recompiling module rvbtb_addr_hash
recompiling module rvbtb_ghr_hash
recompiling module rvrangecheck
recompiling module rveven_paritygen
recompiling module rvecc_encode
recompiling module rvecc_decode
recompiling module ram_16384x39
recompiling module ram_2048x39
recompiling module ram_256x34
50 of 51 modules done
recompiling module ram_64x21
All of 51 modules done
make[1]: Entering directory '/home/zhangkanqi/Cores-VeeR-EH1/tools/csrc'
make[1]: Leaving directory '/home/zhangkanqi/Cores-VeeR-EH1/tools/csrc'
make[1]: Entering directory '/home/zhangkanqi/Cores-VeeR-EH1/tools/csrc'
rm -f csrc*.so pre_vcsobj.so share_vcsobj_.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -no-pie -Wl,--no-as-needed -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -L/usr/lib/x86_64-linux-gnu -L/lib/x86_64-linux-gnu -Wl,--no-as-needed -rdynamic -Wl,-rpath=/opt/tools/Synopsys/VCS-MX2018.09-SP2/linux64/lib -L/opt/tools/Synopsys/VCS-MX2018.09-SP2/linux64/lib objs/amcQw_d.o _1124875_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lnuma -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /opt/tools/Synopsys/VCS-MX2018.09-SP2/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive ./../simv.daidir/vc_hdrs.o /opt/tools/Synopsys/VCS-MX2018.09-SP2/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl
../simv up to date
make[1]: Leaving directory '/home/zhangkanqi/Cores-VeeR-EH1/tools/csrc'
CPU time: 5.336 seconds to compile + .420 seconds to elab + .386 seconds to link
touch vcs-build
./simv +dumpon +vcs+lic+wait -l vcs.log
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Dec 10 17:21 2023
-------------------------
Hello World from VeeR EH1
-------------------------
Finished : minstret = 335, mcycle = 1038
See "exec.log" for execution trace with register updates..
TEST_PASSED
$finish called from file "/home/zhangkanqi/Cores-VeeR-EH1/testbench/tb_top.sv", line 344.
$finish at simulation time 10440
V C S S i m u l a t i o n R e p o r t
Time: 10440
CPU Time: 0.510 seconds; Data structure size: 2.2Mb
Sun Dec 10 17:21:36 2023

zhangkanqi@hwfuzz:~/Cores-VeeR-EH1/tools$ ll
total 16276
-rw-rw-r-- 1 zhangkanqi zhangkanqi 78 12月 10 17:21 console.log
-rw-rw-r-- 1 zhangkanqi zhangkanqi 26688 12月 10 17:21 exec.log
-rw-rw-r-- 1 zhangkanqi zhangkanqi 13922 12月 10 17:21 trace_port.csv
-rw-rw-r-- 1 zhangkanqi zhangkanqi 758 12月 10 17:21 vcs.log
-rw-rw-r-- 1 zhangkanqi zhangkanqi 15582870 12月 10 17:21 verilog.dump
drwxrwxr-x 5 zhangkanqi zhangkanqi 4096 12月 10 17:21 ./
-rw-rw-r-- 1 zhangkanqi zhangkanqi 0 12月 10 17:21 ucli.key
-rw-rw-r-- 1 zhangkanqi zhangkanqi 0 12月 10 17:21 vcs-build
-rw-rw-r-- 1 zhangkanqi zhangkanqi 10980 12月 10 17:21 vcs_compile.log
drwxrwxr-x 4 zhangkanqi zhangkanqi 4096 12月 10 17:21 simv.daidir/
drwxrwxr-x 6 zhangkanqi zhangkanqi 4096 12月 10 17:21 csrc/
-rwxrwxr-x 1 zhangkanqi zhangkanqi 841312 12月 10 17:21 simv*
-rw-rw-r-- 1 zhangkanqi zhangkanqi 1086 12月 10 17:21 vc_hdrs.h
-rw-rw-r-- 1 zhangkanqi zhangkanqi 4088 12月 10 17:21 hello_world.dis
-rw-rw-r-- 1 zhangkanqi zhangkanqi 1763 12月 10 17:21 hello_world.map
-rwxrwxr-x 1 zhangkanqi zhangkanqi 1113 12月 10 17:21 program.hex*
-rwxrwxr-x 1 zhangkanqi zhangkanqi 8876 12月 10 17:21 hello_world.exe*
-rw-rw-r-- 1 zhangkanqi zhangkanqi 1136 12月 10 17:21 hello_world.o
-rw-rw-r-- 1 zhangkanqi zhangkanqi 969 12月 10 17:21 hello_world.cpp.s
drwxrwxr-x 3 zhangkanqi zhangkanqi 4096 12月 10 17:21 snapshots/
drwxrwxr-x 12 zhangkanqi zhangkanqi 4096 12月 10 17:12 ../
-rwxrwxr-x 1 zhangkanqi zhangkanqi 6411 12月 10 16:37 Makefile*
-rwxrwxr-x 1 zhangkanqi zhangkanqi 1369 12月 8 17:05 addassign*
-rwxrwxr-x 1 zhangkanqi zhangkanqi 5550 12月 8 17:05 coredecode*
-rw-rw-r-- 1 zhangkanqi zhangkanqi 67705 12月 8 17:05 JSON.pm
-rwxrwxr-x 1 zhangkanqi zhangkanqi 1877 12月 8 17:05 picmap*
-rwxrwxr-x 1 zhangkanqi zhangkanqi 2884 12月 8 17:05 smalldiv*
-rwxrwxr-x 1 zhangkanqi zhangkanqi 10260 12月 8 17:05 unrollforverilator*
-rw-rw-r-- 1 zhangkanqi zhangkanqi 73 12月 8 17:05 vivado.tcl

[algrobman]

verilog.dump is your VCD waves

[zhangkanqi]

But it doesn't have source code, i can not trace code by clicking.

verilog.dump.zip.zip