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veer.core
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veer.core
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CAPI=2:
name : chipsalliance.org:cores:VeeR_EH1:1.8
filesets:
rtl:
files:
- design/include/veer_types.sv
- design/lib/beh_lib.sv
- design/mem.sv
- design/pic_ctrl.sv
- design/dma_ctrl.sv
- design/ifu/ifu_aln_ctl.sv
- design/ifu/ifu_compress_ctl.sv
- design/ifu/ifu_ifc_ctl.sv
- design/ifu/ifu_bp_ctl.sv
- design/ifu/ifu_ic_mem.sv
- design/ifu/ifu_mem_ctl.sv
- design/ifu/ifu_iccm_mem.sv
- design/ifu/ifu.sv
- design/dec/dec_decode_ctl.sv
- design/dec/dec_gpr_ctl.sv
- design/dec/dec_ib_ctl.sv
- design/dec/dec_tlu_ctl.sv
- design/dec/dec_trigger.sv
- design/dec/dec.sv
- design/exu/exu_alu_ctl.sv
- design/exu/exu_mul_ctl.sv
- design/exu/exu_div_ctl.sv
- design/exu/exu.sv
- design/lsu/lsu.sv
- design/lsu/lsu_bus_buffer.sv
- design/lsu/lsu_clkdomain.sv
- design/lsu/lsu_addrcheck.sv
- design/lsu/lsu_lsc_ctl.sv
- design/lsu/lsu_stbuf.sv
- design/lsu/lsu_bus_intf.sv
- design/lsu/lsu_ecc.sv
- design/lsu/lsu_dccm_mem.sv
- design/lsu/lsu_dccm_ctl.sv
- design/lsu/lsu_trigger.sv
- design/dbg/dbg.sv
- design/dmi/dmi_wrapper.v
- design/dmi/dmi_jtag_to_core_sync.v
- design/dmi/rvjtag_tap.sv
- design/lib/mem_lib.sv
- design/lib/ahb_to_axi4.sv
- design/lib/axi4_to_ahb.sv
- design/veer.sv
- design/veer_wrapper.sv
file_type : systemVerilogSource
includes:
files:
- design/include/build.h : {is_include_file : true}
- design/include/global.h : {is_include_file : true}
file_type : systemVerilogSource
mem_init:
files:
- testbench/hex/hello_world.hex : {copyto : program.hex}
file_type : user
tb:
files:
- testbench/dasm.svi : {is_include_file : true}
- testbench/ahb_sif.sv
- testbench/tb_top.sv
file_type : systemVerilogSource
verilator_tb:
files : [testbench/test_tb_top.cpp : {file_type : cppSource}]
vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]}
targets:
default:
filesets :
- includes
- rtl
- "tool_vivado ? (vivado_tcl)"
lint:
default_tool: verilator
filesets : [includes, rtl]
generate : [veer_default_config]
tools:
verilator :
mode : lint-only
toplevel : veer_wrapper
sim:
default_tool : verilator
filesets :
- includes
- rtl
- mem_init
- tb
- "tool_verilator? (verilator_tb)"
generate : [veer_ahb_config]
tools:
modelsim:
vlog_options :
- -mfcu
- -cuautoname=du
- config/common_defines.vh
rivierapro:
vlog_options :
- config/common_defines.vh
- "-err VCP2694 W1"
compilation_mode : common
verilator:
verilator_options : [--trace, -Wno-fatal]
toplevel : tb_top
synth:
default_tool : vivado
filesets : [includes, rtl, "tool_vivado ? (vivado_tcl)"]
generate : [veer_fpga_config]
tools:
vivado:
part : xc7a100tcsg324-1
pnr : none
toplevel : veer_wrapper
generate:
veer_ahb_config:
generator: veer_config
position : first
parameters:
args : ['-ahb_lite', -unset=assert_on]
veer_default_config:
generator: veer_config
position : first
parameters:
args : [-unset=assert_on]
veer_fpga_config:
generator: veer_config
position : first
parameters:
args : [-unset=assert_on, -set=fpga_optimize=1]
generators:
veer_config:
interpreter: python3
command: configs/veer_config_gen.py
description : Create a VeeR configuration. Note! Only supports the default config