RISC-V Svinval, Svnapot and Svpbmt extensions support

[edubart]

Context

The new RISC-V spec introduces new extensions related to address translations that have potential to optimize TLB, even more so with Hypervisor (issue #60).

• Svnapot - Standard Extension for NAPOT Translation Contiguity: This extension was created to relieve TLB pressure in some scenarios, and might be worth investigating.
• Svpbmt - Standard Extension for Page-Based Memory Types: This extension is related to page specific memory attributes, may not be relevant for us.
• Svinval - Standard Extension for Fine-Grained Address-Translation: This extension can minimize invalidation of TLB entries, and might be worth investigating.

Some of these extensions are already being used by the recent Linux kernel.

Possible solutions

We should read the spec, try to implement, and benchmark if there are any gains in performance. Ideally this should be done after hypervisor (issue #44) and decoder optimization (issue #48), so the CPU margin used by the TLB is less negligible.