[SUGGESTION] -- Hardware information

[hildogjr]

To which part of the project this issue refer to?

• Software
• Data
• Documentation
• Tests
• Other

Suggestion

The project aims to have WiFi, Lora, ... communications but I could found information about the radios. Also, would be interesting for me knows:

1. Specific pin-out of the Raspberry compatible connector (which side is the pin 1? It important for mechanical design of compatible boards);
2. Maximum analog data sample and voltage;
3. Is there any PRU (real time processor/core) for user use? This could be important for some hardware interaction (real time sensors / high sample rates).

[edgarlsitec]

Hello.
I hope everything is covered below and I am happy to answer more questions.

1. Specific pin-out of the Raspberry compatible connector (which side is the pin 1? It important for mechanical design of compatible boards);
   The pin-out of the raspberry compatible connector can be found at the project wiki. The 64bit board is not being sold (yet). We are refining the base board physical design and these parameters are still subject to change. If you need in-depth technical information about something, you can ask exactly what you need here and I will be pleased to answer.
2. Maximum analog data sample and voltage;
   It will be specified at the wiki and a data sheet is being written right now! Soon you will have this information. For instance, I can say that in the final design, the i2c interface will be hardware based and support 400kHz communication. Also, the spi interface currently available at the expansion connector is software based and slow (100kHz clock). But, the final design will have a hardware based spi interface at the expansion header with 1MHz clock. If you need in-depth information about these interfaces or others (PWM, SDIO, I2S, GPIOs) please ask about them.
3. Is there any PRU (real time processor/core) for user use? This could be important for some hardware interaction (real time sensors / high sample rates).
   We are planning to add a FPGA at the final base board release. It will probably be a model from Lattice Semiconductor, I am not sure.