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awesome-opensource-hardware

A curated list of awesome open source hardware tools, generators, and reusable designs.

  • Categorized
  • Alphabetical (per category)
  • Requirements
    • link should be to source code repository
    • open source projects only
    • working projects only (not WIP/rusty)
  • One tag line sentence per project
  • R = Recommended

Table of Contents

PDKs

Compilers

Project

Design and Verification Tools

Designs & Generators

Education

PDKs

Manufacturable PDKs

  • gf180
    • GlobalFoundries 180nm CMOS PDK
  • sg13g2
    • IHP 130nm BiCMOS PDK
  • sky130
    • Skywater 130nm CMOS PDK

Virtual PDKs

Compilers

Build Systems

  • bazelhdl
    • Bazel based hdl build system
  • bender
    • Dependency management tool for hardware projects.
  • chipyard
    • Agile RISC-V SoC Design Framework.
  • cocoon
    • Infrastructure for integrated EDA
  • edalize
    • Abstraction library for interfacing EDA tools.
  • flgen
    • Generate a filelist for EDA tools
  • fusesoc
    • Package manager and build abstraction tool for FPGA/ASIC development.
  • hammer
    • Agile physical design component part of UC Berkeley Chipyard framework.
  • hwtbuildsystem
    • Library of utils for interaction with the vendor tools.
  • legohdl
    • Command line HDL package manager and development tool.
  • mflowgen
    • Build-system generator for ASIC and FPGA design-space exploration.
  • siliconcompiler (R) ⭐
    • Modular distributed build system for hardware

Circuit Compilers

  • abc (R) ⭐
    • System for sequential logic synthesis and formal verification
  • act
    • Asynchronous circuit compiler tools
  • aihwkit
    • IBM Analog Hardware Acceleration Kit
  • amaranth
    • Python based hardware design framework
  • bigspicy
    • Tool for merging circuit descriptions
  • bsc
    • Compiler, simulator, and tools for the Bluespec Hardware Description Language
  • calyx
    • Intermediate language and compilers that generate custom hardware accelerators
  • chisel (R) ⭐
    • Scala based hardware description language
  • circt
    • Circuit IR Compilers and Tools
  • circuitgraph
    • Tools for working with circuits as graphs in python
  • circuitops
    • Infrastructure for dataset generation and model deployment in Generative AI
  • clash
    • Haskell to VHDL/Verilog/SystemVerilog compiler
  • coreir
    • LLVM-style hardware compiler with first class support for generators
  • dfiant
    • Dataflow Hardware Description Language
  • fault
    • Design-for-testing (DFT) Solution
  • finn
    • Dataflow compiler for QNN inference
  • firrtl
    • Intermediate Representation for RTL
  • gamma
    • Optimizes mapping of DNN models on DNN Accelerators
  • gamora
    • Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks
  • ghdl-yosys-plugin
    • VHDL synthesis (based on ghdl)
  • halide
    • Language for fast, portable data-parallel computation
  • halide-to-hardware
    • Hardware generator combining halide and coreir
  • hastlayer
    • VHDL generator from .NET languages (C#, F#, and others) and FPGA framework for .NET hardware acceleration
  • hdl21
    • Hardware Description Library
  • hdlconvertor
    • Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4
  • hs-to-coq
    • Convert Haskell source code to Coq source code
  • ipyxact
    • Python-based IP-XACT parser
  • livehd
    • Infrastructure for live interactive synthesis and simulation
  • llhd
    • Intermediate representation for digital circuit descriptions
  • lsoracle
    • Famework built on EPFL logic synthesis libraries.
  • lstools
    • Showcase examples for EPFL logic synthesis libraries
  • kami
    • Platform for High-Level Parametric Hardware Specification and Verification
  • magma
    • Python based hardware design language
  • matchlib
    • Synthesizable SystemC/C++ library of commonly-used hardware functions
  • matchclib_connections
    • Synthesizable SystemC library implementing latency-insensitive channels
  • mockturtle
    • C++ logic network library
  • myhdl
    • Python based hardware description and verification language
  • naja
    • Structural Netlist API for EDA post synthesis flow development
  • netlist-paths
    • A library and command-line tool for querying a Verilog netlist
  • panda-bambu
    • High level synthesis (HLS) C/C++ framework
  • pipelinec
    • C-like hardware description language (HDL) with automatic pipelining
  • pygears
    • Python based hardware design framework
  • pymtl3
    • Python hardware generation, simulation, and verification framework
  • pyrtl
    • Python integrated design and simulation framework
  • pysysc
    • Python package to make SystemC usable from Python
  • pyverilog
    • Python design toolkit for Verilog HDL
  • rohd
    • Dart based framework for describing and verifying hardware
  • scip
    • Solving Constraint Integer Problems
  • silice
    • Language that simplifies prototyping and writing algorithms on FPGA architectures
  • skidl
    • SKiDL is a module that extends Python with the ability to design electronic circuits
  • slang
    • Library for lexing, parsing, type checking, and elaborating SystemVerilog code
  • sodaopt (R) ⭐
    • Optimizer leveraging mlir to extract, optimize, translate HLSinto LLVM IR
  • spinalhdl
    • Scala based HDL
  • spydrnet
    • Framework for analyzing and transforming Verilog netlists
  • surelog (R) ⭐
    • SystemVerilog IEEE 2017 Pre-processor, Parser, Elaborator, UHDM Compiler
  • sv-parser
    • SystemVerilog IEEE 1800-2017 parser library
  • sv2v (R) ⭐
    • SystemVerilog to Verilog conversion
  • systemc (R) ⭐
    • SystemC system design and verification language that spans hardware and software
  • systemc-compiler
    • Translates synthesizable SystemC to synthesizable Verilog
  • synlig
    • SystemVerilog support for Yosys
  • tapasco
    • Heterogeneous system composer
  • tce
    • Application-specific instruction-set processor (ASIP) toolset
  • uhdm
    • Universal object model for IEEE SystemVerilog designs
  • verible
    • SystemVerilog developer tools, including a parser, style-linter, and formatter
  • veriloggen
    • Mixed-Paradigm Hardware Construction Framework
  • veryl
    • Modern Hardware Description Language based on Rust/SV
  • verik
    • Kotlin based hardware description language
  • vlsir
    • Interchange formats for chip design
  • xls
    • Google framework for hardware synthesis
  • yosys (R) ⭐
    • Yosys Open SYnthesis Suite

FPGA Compilers

  • amf-placer
    • Timing-driven analytical mixed-size FPGA placer
  • dreamplacefpga
    • Analytical Placer for Large Scale Heterogeneous FPGA
  • flowtune
    • FPGA synehsis and PNR optimizer
  • nextpnr
    • FPGA place and route tool
  • vtr (R) ⭐
    • FPGA place and route tool

Layout Compilers

  • align
    • Automatic layout generator for analog circuits
  • autodmp
    • Automated DREAMPlace-based Macro Placement
  • bag
    • Berkeley analog layout generator
  • coriolis
    • RTL2GDS toolchain for mature nodes
  • dreamplace
    • Deep learning toolkit-enabled VLSI placement
  • gdsfactory
    • Platform for chip design and layout
  • gds3d
    • Render GDS files in 3D
  • gdsiistl
    • Converts GDSII files to STL files
  • gdstk
    • C++/Python library for creation and manipulation of GDSII and OASIS files.
  • gdspy
    • Python module for creating GDSII stream files, usually CAD layouts.
  • ieda
    • RTL2GDS infrastructure
  • klayout (R) ⭐
    • Layout viewer
  • kweb
    • Klayout Web Viewer
  • lclayout
    • Layout generator for CMOS standard-cells
  • layout21
    • Integrated Circuit Layout
  • magic
    • Magic VLSI layout tool
  • magical
    • Machine Generated Analog IC Layout
  • openroad (R) ⭐
    • Complete RTL2GDS platform
  • phidl
    • Python GDS layout and CAD geometry creation

Design and Verification Tools

Benchmarks

Board Design

  • boardview
    • Reads KiCAD PCB layout files and writes ASCII Boardview files
  • cuflow
    • Experimental procedural PCB layout program
  • datasheet-scrubber
    • Utility that scrubs PDF datasheets/documents in order to extract key circuit information
  • freecad (R) ⭐
    • 3D parametric CAD for building models of components for KiCad 3D preview (also enclosures)
  • freerouting
    • PCB auto-router
  • kicad (R) ⭐
    • Board design framework
  • kicanvas
    • KiCAD web viewer
  • librepcb
    • Board design framework
  • pcbflow
    • Python based Printed Circuit Board (PCB) layout and design package based on CuFlow

Digital Design

  • digital
    • Digital logic designer and circuit simulator
  • DigSim
    • An interactive digital logic simulator with verilog support (Yosys)
  • verilog-mode
    • Popular free Verilog mode for Emacs
  • vsrtl
    • Visual Simulation of Register Transfer Logic
  • vscode-systemverilog
    • SystemVerilog support in VS Code
  • vscode-teroshdl
    • Full IDE for RTL development in VS Code

Documentation

  • elk
    • Eclipse Layout Kernel - Automatic layout for Java applications.
  • graphviz
    • Python library for graph cration and rendering in DOT language
  • gds3d
    • Reads GDSII layout and renders in 3D
  • hdelk
    • Web-based HDL diagramming tool
  • kythe
    • Verible based SystemVerilog source file indexer
  • memory-layout-diagram
    • Diagrams for memory map layouts
  • netlistsvg
    • Draws an SVG schematic from a JSON netlist
  • netlist-viewer
    • SPICE netlist visualizer
  • nn-svg
    • Publication-ready NN-architecture schematics
  • pcbdraw
    • Convert KiCAD board into 2D drawing suitable for pinout diagrams
  • pinion
    • Generate interactive Diagrams for your PCBs
  • pinout
    • Python package that generates hardware pinout diagrams as SVG images
  • sphinx
    • Document builder
  • sphinx-verilog-domain
    • Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  • sphinxcontrib-hdl-diagrams
    • Sphinx plugin to automatically generate diagrams from RTL.
  • symbolator
    • HDL symbol generator
  • undulate
    • Python compatible wavedrom module with extensions and console rendering support
  • wavedrom (R) ⭐
    • Digital timing diagram rendering engine
  • wavedrompy
    • Python comptabled Wavedrom module

FPGA Design

  • byteman
    • Bitstream relocation and manipulation tool
  • icestudio
    • Visual editor for open FPGA boards
  • f4fpga
    • FPGA toolchain
  • foedag
    • Framework Open EDA Gui
  • logik
    • FPGA toolchain
  • openfpgaloader (R) ⭐
    • Universal utility for programming FPGA
  • rphax
    • Automation flow to develop and prototype hardware accelerators on Xilinx FPGAs

Formal Verification

  • boolector
    • SMT solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions
  • cvc5
    • SMT automatic theorem prover
  • ilang
    • Princeton modeling and Verification Platform for SoCs using ILAs
  • autosva
    • Generates FV testbenches and SVA properties for RTL modules based on interface annotations + GPT4
  • autocc
    • A frontend for JG/SBY to automatically discover covert channels in time-shared hardware
  • pono
    • Extensible SMT-based model checker implemented in C++.
  • sby
    • Front-end for Yosys-based formal verification flows.
  • z3
    • Microsoft research theorem prover

Linters

  • svlint
    • SystemVerilog linter
  • svlint-action
    • GitHub action for svlint
  • verible
    • SystemVerilog developer tools, including a parser, style-linter, and formatter
  • verilator (R) ⭐
    • SystemVerilog simulator and lint system

Register Design

  • gen_registers
    • Python based tool for generating hardware registers and their associated files
  • rggen
    • Configuration and status register generator
  • open-register-design-tool
    • Generate register RTL, models, and docs using SystemRDL or JSpec input
  • peakrdl
    • SystemRDL based control & status register (CSR) toolchain
  • systemrdl
    • Generic compiler front-end for Accellera's SystemRDL 2.0 register description language

Schematics

  • d3-hwschematics
    • Schematic visualizer
  • kaktus2dev
    • Graphical EDA tool based on the IP-XACT standard
  • openplc_editor
    • IDE capable of creating programs for the OpenPLC Runtime
  • oregano
    • Schematic capture and circuit simulator
  • qucs_s
    • Integrated circuit simulator with Graphical User Interface
  • hdl21schematics
    • Hdl21 Schematics
  • xschem
    • Schematic editor for VLSI/Asic/Analog custom designs

Electronics Simulators

  • champsim
    • Trace-based simulator for a microarchitecture study
  • dromajo
    • RISC-V RV64GC functional emulator
  • eesim
    • Browser-based SPICE circuit simulator
  • essent
    • High-performance FIRRTL (Chisel) simulator
  • firesim
    • FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
  • gem5
    • Modular simulator platform for computer-system architecture research
  • muchisim
    • Cycle-level simulator for PPA and cost analysis of distributed multi-chiplet tile-based manycore designs.
  • ghdl (R) ⭐
    • VHDL 2008/93/87 simulator
  • icarus (R) ⭐
    • Verilog IEEE-1364 simulator
  • irsim
    • Switch-level simulator for digital circuits
  • libsystemctlm-soc (R) ⭐
    • SystemC/TLM-2.0 Co-simulation framework
  • logisim-evolution
    • Digital logic design tool and simulator
  • lwtr4sc
    • Transaction recording for SystemC
  • ngspice (R) ⭐
    • Spice simulator
  • noxim
    • Network on Chip Simulator
  • nvc
    • VHDL compiler and simulator
  • pysysc
    • Python package to make SystemC usable from Python
  • qemu (R) ⭐
    • Generic and open source machine & userspace emulator and virtualizer
  • ramulator2
    • Cycle accurate DRAM simulator
  • renode
    • Generic and open source machine emulator
  • sax
    • S-parameter based frequency domain circuit simulation
  • simulide
    • SimulIDE is a simple real-time electronic circuit simulator
  • systemc-components
    • SystemC simulation productivity library
  • tiny-five
    • Lightweight RISC-V emulator and assembler written entirely in Python with examples for AI/ML
  • xictools
    • Circuit simulation package
  • xyce (R) ⭐
    • Parallel spice simulator from Sandia national labs
  • verilator (R) ⭐
    • SystemVerilog simulator and lint system

Verification Frameworks

  • adc-eval
    • Python tools for ADC performance analysis
  • awsteria_infra
    • Middleware for AWS hosted FPGA applications
  • anasysmod
    • Framework for FPGA emulation of mixed-signal systems
  • cocotb
    • Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • cocotbext-axi
    • AXI interface modules for Cocotb
  • cocotbext-pcie
    • PCI express simulation framework for Cocotb
  • constrainedrandom
    • Python package for creating and solving constrained randomization problems
  • cvc
    • CVC: Circuit Validity Checker
  • core-v-verif
    • Functional verification project for the CORE-V family of RISC-V cores
  • ddr5_phy
    • UVM testbench for DDR5 PHY
  • fault
    • Python package for testing hardware
  • force-riscv
    • Instruction Set Generator for RISC-V
  • frame
    • Fast Roofline Analytical Modeling and Estimation
  • fstdumper
    • Verilog VPI module to dump FST (Fast Signal Trace) databases
  • lctime
    • Library cell characterization
  • maestro
    • Analytical cost model evaluating DNN mappings (dataflows and tiling)
  • msdsl
    • Automatic generation of real number models from analog circuits
  • netgen
    • LVS tool for comparing SPICE or verilog netlists
  • openplc_v3
    • OpenPLC Runtime version 3
  • opensta (R) ⭐
    • Signoff quality STA engine used by OpenRoad
  • opentimer
    • High performance static timing analysis
  • openvaf
    • Next generation Verilog-A compiler
  • osvvm
    • A VHDL verification framework
  • pcievhost
    • PCIe (1.0a to 2.0) Virtual host model for verilog
  • pyspice
    • Python interface for ngspice and xyce
  • pyucis
    • Python API to Unified Coverage Interoperability Standard (UCIS) Data
  • pyuvm
    • SystemVerilog UVM written in Python
  • pyvsc
    • Python packages or SystemVerilog UVM style Verification Stimulus and Coverage
  • raft
    • Rapid Abstraction FPGA Toolbox
  • riscv-dv
    • Random instruction generator for RISC-V processor verification
  • rohd-cosim
    • Framework for cosimulation between the ROHD simulator and SystemVerilog simulators.
  • rohd-vf
    • ROHD-based verification and testbench framework in Dart.
  • switchboard (R) ⭐
    • Communication framework for RTL simulation and emulation
  • svreal
    • Synthesizable real number library in SystemVerilog (fixed & floating point formats)
  • systemctlm-cosim-demo
    • Demo system for libsystemctlm-soc library
  • sv_waveterm
    • Generate text waves in simulation log file
  • tvip-apb
    • UVM based AMBA APB VIP
  • tvip-axi
    • UVM based AMBA AXI VIP
  • uvvm
    • Library for making very structured VHDL-based testbenches.
  • v2k-top
    • Parser/simulation framework for Verilog & C++
  • vidbo
    • Virtual development board
  • vunit
    • Unit testing framework for VHDL/SystemVerilog

Physics

  • devsim
    • TCAD Semiconductor Device Simulator
  • elmer
    • Finite Element Solver
  • femwell
    • Finite element based simulation tool for integrated circuits, electric and photonic
  • hotspot
    • Thermal modeling tool for use in architectural studies
  • meep
    • Finite-difference-time-domain (FDTD) electromagneic simulation
  • paraview
    • Data Analysis and Visualization Application
  • pact
    • Thermal simulator
  • scikit-rf
    • RF and Microwave Engineering Scikit

Waveform Viewers

  • scviewer
    • Eclipse plugins to display VCD (e.g. created by SystemC VCD trace).
  • d3wave
    • D3.js based wave (signal) visualizer
  • gtkwave (R) ⭐
    • GTK+ based VCD waveform viewer
  • iio-oscilloscope
    • GTK+ based oscilloscope application for interfacing with various IIO devices
  • konata
    • Instruction pipeline visualizer for Gem5
  • npTDMS
    • Python module for reading TDMS files produced by LabView
  • scopy
    • Software oscilloscope and signal analysis toolset
  • sigrok
    • Portable, signal analysis software suite (logic analyzers, scopes, multimeters, and more)
  • simview
    • Text-based SystemVerilog design browser and waveform viewer
  • sootty
    • Command-line tool for displaying vcd waveforms
  • spyci
    • Python package to parse spice raw data files
  • verilog-vcd-parser
    • Parser for Value Change Dump (VCD) files
  • wavebin
    • Oscilloscope waveform capture viewer and converter
  • waveforms-live
    • Browser based analog waveform viewer

Designs & Generators

Accelerators

  • aes
    • Symmetric block cipher AES (Advanced Encryption Standard)
  • ara
    • Vector Unit, compatible with the RISC-V Vector Extension
  • bfg
    • Compiler for Reduced-Complexity Reconfigurable Fabrics
  • bismp
    • Chisel-based bit-serial matrix multiplication accelerator generator
  • finn
    • Quantized NN to FPGA dataflow accelerator generator
  • fftgenerator
    • MMIO-Based FFT Generator
  • fpu
    • Synthesizable ieee 754 floating point library in verilog
  • garnet
    • CGRA generator
  • gemmini
    • Berkeley Spatial Array Generator
  • gplgpu
    • GPL v3 2D/3D graphics engine in verilog
  • core_jpeg
    • High throughput JPEG decoder in Verilog for FPGA
  • fftgenerator
    • Chisel based FFT generator
  • h265-encoder-rtl
    • H.265 Video Encoder IP Core
  • logicnets
    • Train and generate LUT-based neural networks
  • nngen
    • Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
  • nvdla
    • NVIDIA Deep Learning Accelerator (NVDLA)
  • nyuziprocessor
    • GPGPU microprocessor architecture
  • opencgra
    • Parametrizable Coarse-Grained Reconfigurable Array (CGRA) Generator
  • openofdm
    • 802.11 OFDM PHY decoder
  • openspike
    • Spiking neural network accelerator
  • project-zipline
    • Zipline lossless compression implementation
  • pyfda
    • Python Filter Design Analysis Tool
  • ranc
    • Reconfigurable architecture for neuromorphic computing
  • sha256
    • SHA-256 hash function (NIST FIPS 180-4)
  • sha512
    • SHA-512 hash function (NIST FIPS 180-4)
  • sha3
    • Berkeley SHAR3 ROCC Accelerator
  • serpens
    • HBM FPGA based SpMV Accelerator
  • sextans
    • FPGA accelerator for Sparse-Matrix Dense-Matrix Multiplication (SpMM)
  • spiral
    • Spiral based FFT generator
  • tvm-vta
    • Opwn, modular, deep learning accelerator
  • verigood-ml
    • Verilog Generator, Optimized for Designs for Machine Learning
  • verigpu
    • OpenSource GPU, loosely based on RISC-V ISA
  • verilog-lfsr
    • Parametrizable combinatorial parallel LFSR/CRC module
  • vortex
    • Full-system RISCV-based GPGPU processor

Analog Circuits

  • ams_kgd
    • Repository for Known Good Analog Designs (KGDs)
  • analog_blocks
    • Basic building blocks (OTA, BandGap and LDO) in Skywater 130nm.
  • openfasoc
    • Automated Mixed Signal SoC Synthesis Framework
  • open-pmic
    • Current mode buck converter on the SKY130 PDK

Chip Packaging

  • bsg_packaging
    • Open-Source Hardware Accelerator Packages and Sockets

Boards

Connectivity

  • aib
    • Advanced Interface Bus (AIB) die to die hardware
  • aib-protocols
    • Advanced Interface Bus (AIB) Protocol IP
  • axi
    • AXI SystemVerilog synthesizable IP
  • axi4_aib_bridge
    • AXI4/AIB Bridge RTL
  • bsg_ddr3_io
    • BaseJump DDR3 I/O Design
  • core_ddr3_controller
    • DDR3 memory controller in Verilog for various FPGAs
  • ctucanfd_ip_core
    • CAN with Flexible Data-rate IP Core developed at Department of Measurement of FEE CTU
  • hdmi
    • Send video/audio over HDMI on an FPGA
  • i2c
    • Fully featured implementation of Inter-IC (I2C) bus master
  • idma
    • Modular, parametrizable, and highly flexible Data Movement Accelerator
  • io-gen
    • IO cell generator
  • litedram
    • Small footprint and configurable DRAM (litex)
  • liteeth
    • Small footprint and configurable Ethernet core
  • litescope
    • Small footprint and configurable embedded FPGA logic analyzer
  • litepice
    • Small footprint and configurable PCIe core
  • nocrouter
    • Network-on-Chip Router
  • omi_device_ice
    • Open memory interface example device
  • opencapi_accel
    • OpenCAPI acceleration framework
  • opencapi_client
    • OpenCAPI client reference design
  • openserdes
    • Digitally synthesizable architecture for SerDes using Skywater130
  • pymtl3-net
    • Cornell parameterizable OCN (on-chip network) generator
  • ravenoc
    • Configurable HDL NoC (Network-On-Chip)
  • tnoc
    • Network on Chip Implementation written in SytemVerilog
  • usb3_camera
    • USB C Industrial Camera Project
  • usb_cdc
    • Minimal USB CDC (ACM) implementation in verilog
  • usb_dfu
    • Verilog implementation of the USB Device Class Specification for Device Firmware Upgrade (DFU), version 1.1
  • umi (R) ⭐
    • Universal Memory Interface
  • verilog-axis
    • Verilog AXI stream components for FPGA implementation
  • verilog-ethernet
    • Verilog Ethernet components for FPGA implementation
  • verilog-i2c
    • Verilog I2C interface for FPGA implementation
  • verilog-uart
    • Verilog UART
  • verilog-pcie
    • Verilog PCI express components
  • verilog-wishbone
    • Verilog wishbone components
  • vis4mesh
    • Visualization tool for designing mesh Network-on-Chips
  • vivado-library
    • IP cores and interface definitions compatible with Xilinx Vivado IP Catalog
  • wav-d2d-hw
    • 8lane Wlink with D2D and a single AXI Target/Initiator
  • wav-lpddr-hw
    • DDR (WDDR) Physical interface (PHY) Hardware
  • wav-slink-hw
    • Chiplet link
  • wav-wlink-hw
    • Chiplet link

CPUs

  • a2i
    • A2I POWER processor core RTL (VHDL)
  • ara
    • 64-bit Vector unit coprocessor to Ccva6
  • black-parrot
    • Linux-capable RISC-V multicore
  • cfu-playground
    • Famework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers
  • cores-swerv
    • SweRV EH1 RISC-Vcore
  • cores-swerv-el2
    • SweRV EL2 RISC-V Core
  • core-v-verif
    • Functional verification project for the CORE-V family of RISC-V cores
  • cva6 (R) ⭐
    • Linux capable RISC-V CPU
  • cve2
    • Small two-stage 32 bit RISC-V CPU core (RV32IMC/EMC)
  • cv32e40s
    • RV32IMFCX RISC-V 4-stage secure RISC-V CPU
  • cv32e40x
    • RV32IMFCX RISC-V 4-stage compute RISC-V CPU
  • cvw
    • Configurable RISC-V Processor for RISC-V System-on-Chip Design textbook.
  • ibex (R) ⭐
    • Small 32 bit RISC-V CPU core
  • lizard
    • Cornell modular RV64IM Out-of-Order Processor Built with PyMTL
  • microwatt
    • Open POWER ISA softcore written in VHDL 2008
  • minimax
    • A Compressed-First, Microcoded RISC-V CPU
  • muntjac
    • Simple 64-bit RISC-V multicore processor
  • neorv32
    • Customizable and highly extensible MCU-class 32-bit RISC-V (VHDL)
  • openxiangshan
    • Open-source high-performance RISC-V processor
  • picorv32 (R) ⭐
    • Size-Optimized RISC-V CPU
  • rocket-chip (R) ⭐
    • Linux capable RISC-V Rocket Chip Generator
  • rioschip
    • Out of order RISC-V core
  • serv
    • SErial RISC-V CPU
  • snitch
    • Lean but mean RISC-V system
  • veer
    • 32-bit integer machine-mode RISC-V CPU
  • vroom
    • High performance RISC-V CPU

FPGA Architectures

  • fabulous
    • Fabric generator and CAD tools
  • fabric_team
    • Simple Berkeley FPGA generator class project
  • openfpga
    • FPGA IP Generator
  • prga
    • Open-source FPGA research and prototyping framework

Libraries

  • basejump_stl
    • Library of SystemVerilog components
  • basic_verilog
    • Library of SystemVerilog components
  • berkeley-hardfloat
    • Berkeley hardware floating point units
  • common_cells
    • Library of SystemVerilog components
  • cvfpu
    • Parametric floating-point unit
  • hdl
    • Library of Analog Deveices specific components
  • lambdalib (R) ⭐
    • Hardware abstraction library
  • lambdapdk (R) ⭐
    • Library of open source Process Design Kits (PDKs)
  • libsv
    • Parameterized SystemVerilog digital hardware library
  • mathlib
    • SystemVerilog MathLib
  • oh (R) ⭐
    • Library of Verilog components
  • pztb-core
    • Collection of class libraries for testbench development
  • pzbcm
    • Basic common modules
  • rohd-hcl
    • Library of reusable & configurable hardware components developed with ROHD
  • vlsiffra
    • Fast and efficient standard cell based adders, multipliers and multiply-adders

Memory

  • core_axi_cache
    • 128KB AXI cache (32-bit in, 256-bit out)
  • cv-hpdcache
    • High-Performance L1 Dcache
  • bsg_fakeram
    • Fake RAM generator
  • huancun
    • Open-source high-performance non-blocking cache
  • openram
    • Static random access memory (SRAM) compiler.
  • lake
    • Synthesizable memory generator

Systems

  • caliptra
    • Caliptra Root of Trust Architecture
  • caliptra-rtl
    • Caliptra Root of Trust (RTL)
  • beagle_sdr_gps
    • KiwiSDR: BeagleBone web-accessible GPS/SDR
  • bsg_manycore
    • Tile based architecture designed for computing efficiency, scalability
  • cep
    • RISC-V based Common Evaluation Platform (CEP)
  • esp
    • Heterogeneous SoC architecture and IP design platform
  • falcon
    • Fast Analysis of LTE Control channels
  • hero
    • FPGA-based research platform for heterogeneous design
  • litex
    • SoC builder framework
  • openfasoc
    • Open Source FASOC generators
  • openpiton
    • General purpose, multithreaded manycore processor
  • opentitan
    • Open source silicon root of trust
  • openwifi-hw
    • IEEE 802.11 WiFi baseband FPGA (chip) design
  • pulp
    • Multicore RISC-V based SoC
  • pulpissimo
    • Single core RISC-V based SoC
  • rose
    • Unified simulation platform for robotic systems
  • senseq
    • Mixed-signal system on chip for nanopore-based DNA sequencing
  • verilogboy
    • Game Boy compatible machine with Verilog
  • wulpus
    • Wearable low-power ultrasound probe
  • x-heep
    • Extendable and configurable RISC-V SoC

Boards

Education

Analog Design

  • book-on-mos-stagse
    • Analysis and Design of Elementary MOS Amplifier Stages
  • SiliWiz
    • Browser based interactive circuit design tool.

Board Design

Digital Design

FPGA Design

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