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Transferring empty outer lists at lower complexities #224

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matthijsr opened this issue Mar 26, 2022 · 0 comments
Open

Transferring empty outer lists at lower complexities #224

matthijsr opened this issue Mar 26, 2022 · 0 comments
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@matthijsr
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Background

https://abs-tudelft.github.io/tydi/specification/physical.html#last-signal-description

[C<4] It is illegal to assert a last bit for dimension j without also asserting the last bits for dimensions j′<j in the same lane.

[C<4] It is illegal to assert the last bit for dimension 0 when the respective data lane is inactive, except for empty sequences.

The first rule suggests that at C<4, and (as an example) D=3, it is not possible to assert last="100" or last="110", or last="010").

Issue

This means that at C<4, it is illegal to transfer empty outer lists, which in turn means that Stream complexity has an effect on the kinds of data transferred.

For instance, the example given in the last signal description for C≥8, D=2
["Hello", "World"], ["Tydi", "is", "nice"], [""], []
makes use of an empty outer list (the last element, []). This requires asserting last="10".

Suggested Fix

It is not clear whether this is intentional. However, I am of the opinion that Stream properties should not affect the kind of data which can be transferred.

As such, I recommend amending the first rule in the Background section of this issue to also include an exception for empty sequences.

@mbrobbel mbrobbel added the 🐬 specification Item related to the specification label Mar 28, 2022
@mbrobbel mbrobbel changed the title [Spec] Transferring empty outer lists at lower complexities Transferring empty outer lists at lower complexities Mar 28, 2022
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