{"payload":{"header_redesign_enabled":false,"results":[{"id":"214885806","archived":false,"color":"#427819","followers":474,"has_funding_file":false,"hl_name":"Xilinx/Vitis_Accel_Examples","hl_trunc_description":"Vitis_Accel_Examples","language":"Makefile","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":214885806,"name":"Vitis_Accel_Examples","owner_id":3189299,"owner_login":"Xilinx","updated_at":"2024-01-12T17:39:25.412Z","has_issues":true}},"sponsorable":false,"topics":["zynq","xilinx","soc","alveo","fpga-programming","acap","vitis"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":60,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AXilinx%252FVitis_Accel_Examples%2B%2Blanguage%253AMakefile","metadata":null,"csrf_tokens":{"/Xilinx/Vitis_Accel_Examples/star":{"post":"9-h60sfI_wXeQ9VCxYimO-XRrXoP6EXyM6P2tUzipliqq0MpQucov9TI-rw3fQbl0mnt87UOIPxRokI1vrY6PA"},"/Xilinx/Vitis_Accel_Examples/unstar":{"post":"aJHmH_YY4J5QlNT3O1D-Z6dqhFt5q1DTAmQT1DFcmiHTUveotsxm0vMiRE9smMJYPl4QvWwgUIJNNqQCGRba8w"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"R7v0wIp-XpAfd1VHjlA1dMAHvf_01lusNyjf_jCcB_VcfNvjWo-IHb82TGgWI52Q1kVgULC4he6c9yFkqFKMWA"}}},"title":"Repository search results"}