{"payload":{"header_redesign_enabled":false,"results":[{"id":"169208857","archived":false,"color":"#DAE1C2","followers":327,"has_funding_file":false,"hl_name":"WangXuan95/USTC-RVSoC","hl_trunc_description":"An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":169208857,"name":"USTC-RVSoC","owner_id":20251744,"owner_login":"WangXuan95","updated_at":"2023-09-14T13:00:32.919Z","has_issues":true}},"sponsorable":false,"topics":["cpu","fpga","riscv","rtl","verilog","systemverilog","soc","risc-v","rv32i","softcore"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":73,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AWangXuan95%252FUSTC-RVSoC%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/WangXuan95/USTC-RVSoC/star":{"post":"5eL8GGn4vNRttQlhe1yvwfjIKU2U1AnE5kMNTPlguEHRAmQ6sUkLZJ9FLoV3JKWxZDufW1kZo7zxG0gVmGMJlw"},"/WangXuan95/USTC-RVSoC/unstar":{"post":"esBzYNG92h63rYFyHjUlBxZw177UVnskswzbblPC0yl4A0tN9NV0ZmHU3_ks96AQez6U_64Ma7ugSMmFEHDlwA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"tmcGZByg4QTYYHM-fk7DMVh4gGpvEh1_kT2KJLjxL7x7s-ueU_rmAHiJbwmsiACi4qkec1n-fhnKq3SIZwRr9A"}}},"title":"Repository search results"}