UH-JLS/RTL_develop_ver at main · WangXuan95/UH-JLS · GitHub

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README.md		README.md
acgen.sv		acgen.sv
bitpacker1.sv		bitpacker1.sv
bitpacker2.sv		bitpacker2.sv
bitpacker3.sv		bitpacker3.sv
bypass.sv		bypass.sv
channelpacker.sv		channelpacker.sv
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issue.sv		issue.sv
linebuf.sv		linebuf.sv
merge.sv		merge.sv
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uh_jls.sv		uh_jls.sv

README.md

This is a development version that can reach a frequency of 185MHz.

It currently only supports the "Pseudo-LS" manner described in the paper [1], so it is slightly lossy (rather than lossless).

It have no known functional bugs, but the code is written in SystemVerilog (not Verilog) and is not very standardized.

When I have time, I will modify it to both "Lossless" manner and "Pseudo-LS" manner, and let it be the stable version.

　

[1] Xuan Wang, Lei Gong, Chao Wang, Xi Li, Xuehai Zhou : UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression. ICCD 2021: 335-343