{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":341099147,"defaultBranch":"main","name":"FPGA-FOC","ownerLogin":"WangXuan95","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2021-02-22T06:16:41.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/20251744?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1613974729.0586271","currentOid":""},"activityList":{"items":[{"before":"2d78fdd30a51ece5f8c40e4efa793132623bd04e","after":"3816c6c08f0cab4ff61e9ce9ff829c9f25b62cb3","ref":"refs/heads/main","pushedAt":"2023-09-15T01:27:53.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"WangXuan95","name":"X.Wang","path":"/WangXuan95","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20251744?s=80&v=4"},"commit":{"message":"add license","shortMessageHtmlLink":"add license"}},{"before":"33eb8bb9e93c0a99c4132f63bfd3f9980c27b6b4","after":"2d78fdd30a51ece5f8c40e4efa793132623bd04e","ref":"refs/heads/main","pushedAt":"2023-06-09T13:38:49.030Z","pushType":"push","commitsCount":1,"pusher":{"login":"WangXuan95","name":"X.Wang","path":"/WangXuan95","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20251744?s=80&v=4"},"commit":{"message":"update README","shortMessageHtmlLink":"update README"}},{"before":"797f6ef3266fe29d8f2331173eb76a499b1702de","after":"33eb8bb9e93c0a99c4132f63bfd3f9980c27b6b4","ref":"refs/heads/main","pushedAt":"2023-06-09T12:55:46.434Z","pushType":"push","commitsCount":1,"pusher":{"login":"WangXuan95","name":"X.Wang","path":"/WangXuan95","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20251744?s=80&v=4"},"commit":{"message":"change to Verilog2001","shortMessageHtmlLink":"change to Verilog2001"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAADgQ-ndAA","startCursor":null,"endCursor":null}},"title":"Activity · WangXuan95/FPGA-FOC"}