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Perf counters #388

Merged
merged 20 commits into from Mar 26, 2024
Merged

Perf counters #388

merged 20 commits into from Mar 26, 2024

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jjjt-git
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Fixes #361
Not tested, because I did not find the time for it.
So I do not know, whether it works or not.

@Dolu1990
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Dolu1990 commented Feb 5, 2024

Hi,

One thing would be to preserve backward compatibility, i mean in particualr the mcycleAccess = CsrAccess.NONE, and others.

Idea being to preserve that feature there, while also havig the possibility to have it implemented by your plugin :)

@jjjt-git
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jjjt-git commented Feb 5, 2024

I added the legacy counters back in, but made sure, they will not be generated if a CounterService is part of the pipeline.
I still have not tested the CounterPlugin, but hope to get to that later that week...

@Dolu1990
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Dolu1990 commented Feb 6, 2024

Ok thanks :)

@jjjt-git
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The Plugin works.

@@ -122,12 +122,8 @@ object VexRiscvAhbLite3{
mscratchGen = false,
mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.READ_ONLY,
mcycleAccess = CsrAccess.NONE,
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Would it be possible to still keep those option ?
I know that would be redundant to the CounterPlugin implementation, but that would preserve backward compatibility without any disruption. (not break users setups)

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(this is a general comment, so would also apply for the other demo)

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The options are still available in the CSRPlugin. I removed them from here and other places, since CsrAccess.NONE was and is the default value for these.

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Would be possible to revert all the removals of "mcycleAccess = CsrAccess.NONE" and similar things ?

They are there to make it clear to the user that it isn't included, and that if they want they can just turn it on there.

@@ -150,7 +150,7 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
plic.addTarget(core.cpu.externalSupervisorInterrupt)
List(clint.logic, core.cpu.logic).produce {
for (plugin <- core.cpu.config.plugins) plugin match {
case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time
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Same here, would need to preserve that feature in the CsrPlugin. (even if that is a duplication) to not break people code

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The feature is still in CSRPlugin, even if disabled when CounterService is present (which in this demo it is), so it should break no existing code which uses the Counters in CsrPlugin.

@jjjt-git
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I reverted the removal of the config options.
The GenFull still uses the CounterPlugin, as does the VexRiscvAxi4LinuxPlicClint.
However there is (currently) no module in the repo to provide performance counters. It should be quite simple to add to the various cache-modules, but I have not looked into it yet.

@Dolu1990 Dolu1990 changed the base branch from master to dev March 22, 2024 08:00
@Dolu1990
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Thanks ^^
The pr seems all good to me, i just updated it to go into dev instead of master.

Also note since november i'm working on VexiiRiscv :
https://github.com/SpinalHDL/VexiiRiscv

medium / long terms the idea is to migrate toward it.
Let's me know if you are interrested into the project ^^

@@ -649,7 +654,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
pipeline.update(MPP, UInt(2 bits))

if(withExternalMhartid) externalMhartId = in UInt(mhartidWidth bits)
if(utimeAccess != CsrAccess.NONE) utime = in UInt(64 bits) setName("utime")
if(pipeline.serviceExist(classOf[CounterService]) && utimeAccess != CsrAccess.NONE) utime = in UInt(64 bits) setName("utime")
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Ahhh this seems broken, shouldn't it be !pipeline.serviceExist(classOf[CounterService]) ?

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Yes, this must have slipped by.

@jjjt-git
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Fixed the condition.

@Dolu1990 Dolu1990 merged commit 0e4032c into SpinalHDL:dev Mar 26, 2024
@Dolu1990
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Thanks ^^

@jjjt-git
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my pleasure

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RiscV Counters
3 participants