Some define can not find out in std lib like SPI_SR_BSY_Pos SPI_SR_RXNE_Pos please teach me which file them included

[y5664579]

Thx for your hard work，beyond all praise.

[y5664579]

And used stm32f103 maybe them is stm32f407 included. How can I use them on stm32f103?

[RobertoBenjami]

• f103: Project directory/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h (or other header file)
• f407: Project directory/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h (or other header file)

This file contains these macros.

[y5664579]

• Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h

thank you very much.
I found them in the head file which cube maked, but I never use cube lol.

[y5664579]

• f103: Project directory/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h (or other header file)
• f407: Project directory/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h (or other header file)

This file contains these macros.

Maybe a std lib version will be nice lots of stm32f like chip used std lib.

[RobertoBenjami]

Your CMSIS version is very old.

stm32f10x.h version V3.5.0 (date 11-March-2011):
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty /
#define SPI_SR_TXE ((uint8_t)0x02) /!< Transmit buffer Empty /
#define SPI_SR_CHSIDE ((uint8_t)0x04) /!< Channel side /
#define SPI_SR_UDR ((uint8_t)0x08) /!< Underrun flag /
#define SPI_SR_CRCERR ((uint8_t)0x10) /!< CRC Error flag /
#define SPI_SR_MODF ((uint8_t)0x20) /!< Mode fault /
#define SPI_SR_OVR ((uint8_t)0x40) /!< Overrun flag /
#define SPI_SR_BSY ((uint8_t)0x80) /!< Busy flag */

stm32f10xb.h version V4.2.0 (date 31-March-2017):
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 /
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /!< 0x00000002 /
#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /!< 0x00000008 /
#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /!< 0x00000020 /
#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /!< 0x00000040 /
#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /!< 0x00000080 /
#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag */