README.md

Single Cycle CPU with 2-way Set associative Cache

All logic circuits are Flip-Flop

Architecture Overview

Brief version

Detail version (More Detail)

Support Instruction

• add, sub, and, xor
• mul(multi-cycle bitwise operation)
• addi, slli, srai, slti
• beq, bge, bne, blt
• lw, sw
• auipc
• jal, jalr
• ecall(system call for end of program)

Memory

• Size: 16KB
• Data Width: 32 bits

Read(Delay 10 cycles)

Write(Delay 5 cycles)

Cache

• Size: 256 Bytes(0.25KB)
• Data Width: 128 bits
• Associative: 2-way
• Replacement policy: LRU
• Write hit policy: write back
• Write miss policy: write allocate
• Address Segmentation: 25 bits for tag, 3 bits for index, 4 bits for offset

Finite State Machine Schematic Diagram

Data Transportation

Performance(the execution cycle number of each instruction set)

• I0: leaf program (Python) (Assembly)
• I1: Factorial (Python) (Assembly)
• I2: Recursive relation function (Python) (Assembly)
• I3: Bubble sort (Python) (Assembly)
• IH: Same as I3 but with 101 elements (Rank: 3 / 75)

Consider finally store data back to memory

cycle time: 10ns / cycle

Instruction Set	Without Cache	Direct Mapped	2-way Set Associative	Speed up
I0	78	76	76	1.02
I1	463	367	367	1.26
I2	437	375	375	1.16
I3	1359	455	440	3.08
IH	384435	100240	104104	3.83