Last port of module rendered red

[fenhl]

When the closing paren is on its own line, the last port of a module declaration is highlighted in red:

module Id(
    input in,
    output out
);
    assign out = in;
endmodule

As you can see, github has the same bug, except it uses green instead of red.

[emroch]

This happens only in the case of the last line being "output <port_name>" with no other (non-whitespace) characters on the line. If you add a comment, a range, or a second port name, the highlighting is correct. In the below examples, the first one is rendered wrong (red), while the other three are rendered correctly.

module sync (
    input clk, d,
    output q
  );
endmodule

module sync (
    input clk, d,
    output q        //
  );
endmodule

module sync (
    input clk, d,
    output [1:0] q
  );
endmodule

module sync (
    input clk, d,
    output q, p
  );
endmodule