hello_led.ipynb

{
 "cells": [
  {
   "cell_type": "code",
   "execution_count": 1,
   "metadata": {
    "collapsed": true
   },
   "outputs": [],
   "source": [
    "from __future__ import absolute_import\n",
    "from __future__ import print_function\n",
    "import sys\n",
    "import os\n",
    "from veriloggen import *"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "metadata": {
    "collapsed": true
   },
   "outputs": [],
   "source": [
    "def mkLed():\n",
    "    m = Module('blinkled')\n",
    "    width = m.Parameter('WIDTH', 8)\n",
    "    clk = m.Input('CLK')\n",
    "    rst = m.Input('RST')\n",
    "    led = m.OutputReg('LED', width, initval=0)\n",
    "    count = m.Reg('count', 32, initval=0)\n",
    "\n",
    "    seq = Seq(m, 'seq', clk, rst)\n",
    "\n",
    "    seq.If(count == 1024 - 1)(\n",
    "        count(0)\n",
    "    ).Else(\n",
    "        count.inc()\n",
    "    )\n",
    "\n",
    "    seq.If(count == 1024 - 1)(\n",
    "        led.inc()\n",
    "    )\n",
    "\n",
    "    seq(\n",
    "        Systask('display', \"LED:%d count:%d\", led, count)\n",
    "    )\n",
    "\n",
    "    return m"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 3,
   "metadata": {},
   "outputs": [],
   "source": [
    "def mkTest():\n",
    "    m = Module('test')\n",
    "\n",
    "    # target instance\n",
    "    led = mkLed()\n",
    "\n",
    "    uut = Submodule(m, led, name='uut')\n",
    "    clk = uut['CLK']\n",
    "    rst = uut['RST']\n",
    "\n",
    "    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'\n",
    "    simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)\n",
    "    simulation.setup_clock(m, clk, hperiod=5)\n",
    "    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)\n",
    "\n",
    "    init.add(\n",
    "        Delay(1000 * 100),\n",
    "        Systask('finish'),\n",
    "    )\n",
    "\n",
    "    return m"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\n",
      "\n",
      "module test\n",
      "(\n",
      "\n",
      ");\n",
      "\n",
      "  localparam WIDTH = 8;\n",
      "  reg CLK;\n",
      "  reg RST;\n",
      "  wire [WIDTH-1:0] LED;\n",
      "\n",
      "  blinkled\n",
      "  uut\n",
      "  (\n",
      "    .CLK(CLK),\n",
      "    .RST(RST),\n",
      "    .LED(LED)\n",
      "  );\n",
      "\n",
      "\n",
      "  initial begin\n",
      "    $dumpfile(\"uut.vcd\");\n",
      "    $dumpvars(0, uut, CLK, RST, LED);\n",
      "  end\n",
      "\n",
      "\n",
      "  initial begin\n",
      "    CLK = 0;\n",
      "    forever begin\n",
      "      #5 CLK = !CLK;\n",
      "    end\n",
      "  end\n",
      "\n",
      "\n",
      "  initial begin\n",
      "    RST = 0;\n",
      "    #100;\n",
      "    RST = 1;\n",
      "    #100;\n",
      "    RST = 0;\n",
      "    #100000;\n",
      "    $finish;\n",
      "  end\n",
      "\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n",
      "\n",
      "module blinkled #\n",
      "(\n",
      "  parameter WIDTH = 8\n",
      ")\n",
      "(\n",
      "  input CLK,\n",
      "  input RST,\n",
      "  output reg [WIDTH-1:0] LED\n",
      ");\n",
      "\n",
      "  reg [32-1:0] count;\n",
      "\n",
      "  always @(posedge CLK) begin\n",
      "    if(RST) begin\n",
      "      count <= 0;\n",
      "      LED <= 0;\n",
      "    end else begin\n",
      "      if(count == 1023) begin\n",
      "        count <= 0;\n",
      "      end else begin\n",
      "        count <= count + 1;\n",
      "      end\n",
      "      if(count == 1023) begin\n",
      "        LED <= LED + 1;\n",
      "      end \n",
      "      $display(\"LED:%d count:%d\", LED, count);\n",
      "    end\n",
      "  end\n",
      "\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n",
      "VCD info: dumpfile uut.vcd opened for output.\n",
      "LED:  x count:         x\n",
      "LED:  x count:         x\n",
      "LED:  x count:         x\n",
      "LED:  x count:         x\n",
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      "LED:  x count:         x\n",
      "LED:  x count:         x\n",
      "LED:  x count:         x\n",
      "LED:  x count:         x\n",
      "LED:  0 count:         0\n",
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      "\n"
     ]
    }
   ],
   "source": [
    "if __name__ == '__main__':\n",
    "    test = mkTest()\n",
    "    verilog = test.to_verilog(filename='tmp.v')\n",
    "    #verilog = test.to_verilog()\n",
    "    print(verilog)\n",
    "\n",
    "    sim = simulation.Simulator(test)\n",
    "    rslt = sim.run()\n",
    "    print(rslt)\n",
    "\n",
    "    # sim.view_waveform()"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {
    "collapsed": true
   },
   "outputs": [],
   "source": []
  }
 ],
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