{"payload":{"header_redesign_enabled":false,"results":[{"id":"102515882","archived":false,"color":"#DAE1C2","followers":102,"has_funding_file":false,"hl_name":"OPAE/intel-fpga-bbb","hl_trunc_description":"Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs","language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":102515882,"name":"intel-fpga-bbb","owner_id":30705801,"owner_login":"OPAE","updated_at":"2024-02-22T21:46:54.178Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":68,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AOPAE%252Fintel-fpga-bbb%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/OPAE/intel-fpga-bbb/star":{"post":"ZmtH2p85ROXKiSIL3eqWiAcqMK-gcbVioZsR_bqay53yvtDFH1q0MbYcV8Db5LFxVkczyd_OhXIRRcTtAXcaNQ"},"/OPAE/intel-fpga-bbb/unstar":{"post":"Idf2xsMds8YYRNm1sCvSezzAIXyMus5YRcOIonA9eB_QZr1jCsP2PURTrm3fho19dfC1OUSOf-Um4_2moNKEsg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"FujPX1hB4JOsvg_emxwi4n2YqIiv7kmINdd8Hj6ZQVcCjNoB9qIY8fkq1PehpoykCgnFBUydSlx74fwA0j3eww"}}},"title":"Repository search results"}