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Publication

Journal Publications

Conference Publications

  • Olivia. Chen, "Extremely Energy-efficient Deep Learning Hardware using Adiabatic-flux-quantum Technology (Electronics)", Young Scientist Plenary, 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018. (invited)
  • O. Chen, T. Tanaka, C.L. Ayala, N. Takeuchi and N. Yoshikawa, "Design of Adiabatic-Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018.
  • O. Chen, X. Ma, Y. Wang, N. Takeuchi and N. Yoshikawa, "Design and implementation of an extremely energy-efficient deep learning accelerator using superconducting logic", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018.
  • C. Fourie, M. Botha, P. Febvre, C.L. Ayala, Q. Xu, N. Yoshikawa, E. Patrick, M. Law, Y. Wang, M. Annavaram, P. Beerel, S. Gupta, S. Nazarian and M. Pedram, "ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018. (invited)
  • T. Tanaka, C.L. Ayala, O. Chen, R. Saito and N. Yoshikawa, "Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018.
  • Y. He, N. Takeuchi, Q. Xu and N. Yoshikawa, "Superconducting microwave delay network for adiabatic quantum-flux-parametron logic", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018.
  • N. Takeuchi, C.L. Ayala, O. Chen and N. Yoshikawa, "A feedback-friendly large-scale clocking scheme for adiabatic quantum-flux-parametron logic datapaths", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018.
  • C.L. Ayala, O. Chen, R. Saito, T. Tanaka, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "Execution units for a RISC-based adiabatic quantum-flux-parametron microprocessor datapath", 2018 Applied Superconductivity Conference (ASC 2018), Seattle, US, Oct. 2018.
  • O. Chen, Y. Wang, N. Takeuchi and N. Yoshikawa, "Design and Evaluation of Deep Learning Accelerator using Superconductor Logic Families", IEICE Society Conference 2018, Kanazawa University, Kanazawa, Japan, Sept. 2018.
  • C.L. Ayala, O. Chen and N. Yoshikawa, "Comprehensive Automated Timing Extraction Methodology for Characterizing an Adiabatic Quantum-Flux-Parametron Logic Cell Library", IEICE Society Conference 2018, Kanazawa University, Kanazawa, Japan, Sept. 2018.
  • T. Tanaka, C.L. Ayala, Q. Xu and N. Yoshikawa, "遺伝的アルゴリズムを用いた断熱型量子磁束パラメトロン集積回路の自動設計", IEICE Society Conference 2018, Kanazawa University, Kanazawa, Japan, Sept. 2018.
  • T. Tanaka, C.L. Ayala, Q. Xu, R. Saito and N. Yoshikawa, "Design of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automated Placement Tool Based on Genetic Algorithms", IEICE Tech. Rep., vol. 118, no. 178, SCE2018-16, pp. 53-57, Aug. 2018.
  • N. Takeuchi, C. Ayala, Q. Xu, Y. Yamanashi and N. Yoshikawa, “Current Progress in Adiabatic Quantum Flux Parametron,” The 30th International Symposium on Superconductivity (ISS 2017), Iino Hall and Conference Center, Tokyo, Dec. 2017. (invited)
  • Q. Xu, C. L. Ayala, N. Takeuchi and N. Yoshikawa, "Design and implementation of AQFP-based register files for an AQFP 4-bit RISC microprocessor prototype", 2017 Europe Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, 2017.
  • N. Yoshikawa, N. Takeuchi, C.L. Ayala, Q. Xu, K. Fang, N. Tsuji, F. China, Y. Murai, T. Ortlepp, Y. Yamanashi, "Recent research developments of adiabatic quantum-flux-parametron circuits　technology toward energy-efficient high-performance computing", 017 Europe Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, 2017. (invited)
  • Q. Xu, C. L. Ayala, Y. Murai, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "Performance Analysis of Synthesized Benchmark Circuits Implemented in Adiabatic Superconductor Logic", Proc. of International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, 2017.
  • C. L. Ayala, Q. Xu, Y. Murai, R. Saito, N. Takeuchi, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, "A Large-Scale Design Flow for Adiabatic Quantum-Flux-Parametron Circuits with Retiming and Fan-out Deconstruction", Proc. of International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, 2017.
  • Q. Xu, C. L. Ayala, Y. Murai, N. Takeuchi, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, "Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation with HDL Backend Verification", 2016 Applied Superconductivity Conference (ASC 2016), Denver, USA, 2016.
  • N. Takeuchi, C. Ayala, Q. Xu, F. China, N. Tsuji, T. Narama, T. Ortlepp, Y. Yamanashi, and N. Yoshikawa, “Recent Progress towards Energy-Efficient Microprocessors Using AQFP Logic,” The 5th International Conference on Superconductivity and Magnetism (ICSM 2016), Fethiye, Turkey, Apr. 2016 . (invited)
  • N. Takeuchi, C. L. Ayala, Q. Xu, F. China, N. Tsuji, T. Ando, Y. Murai, K. Fang, T. Ortlepp, Y. Yamanashi, and N. Yoshikawa, “A Review of Current Progress of Adiabatic Quantum-Flux-Parametron Logic,” The 9th Superconducting SFQ VLSI Workshop (SSV2016), Yokohama National University, Kanagawa, Aug. 2016. (invited)
  • Q. Xu, C.L. Ayala, Y. Yamanashi and N. Yoshikawa, "HDL-based Modelling Approach for Adiabatic Superconductor Logic Simulation", IEICE Tech. Rep., vol. 115, no. 412, SCE2015-38, pp. 11-15, Jan. 2016.
  • Q. Xu, C. L. Ayala, N. Takeuchi, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, "Creation of a Logic Simulation Model for Adiabatic Quantum Flux Parametron Logic", 2015 Europe Conference on Applied Superconductivity (EUCAS 2015), Lyon, France, 2015.
  • C.L. Ayala, N. Takeuchi, Q. Xu, T. Narama, Y. Yamanashi, T. Ortlepp and N. Yoshikawa, "Timing Extraction for Logic Simulation of VLSI Adiabatic Quantum-Flux-Parametron Circuits", IEICE Tech. Rep., vol. 115, no. 242, SCE2015-21, pp. 7-12, Oct. 2015.
  • Q. Xu, C.L. Ayala, N. Takeuchi, T. Ortlepp, Y. Yamanashi and N. Yoshikawa, "Design of an Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic and Its Digital Modeling Approach", IEICE Tech. Rep., vol. 115, no. 173, SCE2015-16, pp. 47-51, Aug. 2015.
  • Q. Xu, Y. Yamanashi, CL. Ayala, N. Takeuchi, T. Ortlepp and N. Yoshikawa, "Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic", Proc. of 15th International Superconductive Electronics Conference (ISEC 2015), Nogoya, Japan, 2015.
  • Q. Xu, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, “High-speed Demonstration of Bit-serial SFQ-based Computing for Integer Iteration Algorithms,” Cryogenics and Superconductivity Society of Japan, Tokyo, 2014.
  • Q. Xu, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, “High-speed Demonstration of a Single-Flux-Quantum Processor for Solving the 3n + 1 Problem,” 27th International Symposium on Superconductivity, Tokyo, 2014.
  • Q. Xu, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, "Demonstration of bit-serial SFQ-based computing for integer iteration algorithms", 2014 Applied Superconductivity Conference (ASC 2014), Charlotte, USA, 2014.
  • Q. Xu, Y. Shimamura, Y. Yamanashi, N. Yoshikawa and T. Ortlepp, "Analysis of computational energy efficiency in single-flux-quantum electronics by implementing an integer-based hardware-algorithm", Proc. of 14th International Superconductive Electronics Conference (ISEC2013), Boston, USA, 2013.

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