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I noticed in the constraints a multicycle path of 2 for the FX3 input path between the PCLK input and its -500ps phase delayed internal clock. I don't see the logic for implemented for a multicycle path, so I am curious if the constraint is actually valid here.
Can you shed some light on this?
The text was updated successfully, but these errors were encountered:
I noticed in the constraints a multicycle path of 2 for the FX3 input path between the PCLK input and its -500ps phase delayed internal clock. I don't see the logic for implemented for a multicycle path, so I am curious if the constraint is actually valid here.
Can you shed some light on this?
The text was updated successfully, but these errors were encountered: