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RISC-V: Support for WCH/QingKe XW extension #6385
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Ghidra suports user customization for instruction set extensions like WCH/QingKe. You would have to learn a little about how Ghidra's sleigh system works, patch a few files released Ghidra files under You might break down the issue into steps something like these:
The final step is to help the Ghidra developers decide how much of this should be included in the Ghidra release everyone gets, how much they should enable with extensions to the |
Thank you, that was very helpful. I've made a PR with my very preliminary implementation. |
Their openocd fork has been successfully GPL lettered out of the MRS multiple times. |
Is your feature request related to a problem? Please describe.
The WCH/QingKe RISC-V cores have an "XW" extension implementing a small number of additional compressed 16-bit opcodes. Unfortunately, these opcodes conflict with some standard ones, which causes incorrect disassembly and even more incorrect decompilation. I would like to see Ghidra support for this extension.
The opcode encodings don't seem to be properly documented, so I figured them out here
Describe the solution you'd like
I'm not at all familiar with how Ghidra works internally, but I'd like to see "XW" as its own variant of RISC-V.
Additional context
The manual for the QingKe V4 core can be found here, but it only contains a single sentence about the "XW" extension which doesn't explain anything about how it works in detail.
The vendor toolchain for these cores is here, but the source code to their GCC patches does not seem to be available. If you want only GCC, there are Windows binaries here. If you want macOS binaries, there are some here (direct link). Note that objdump doesn't seem to properly disassemble their own extension (even though GAS accepts it).
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