{"payload":{"header_redesign_enabled":false,"results":[],"type":"repositories","page":1,"page_count":0,"elapsed_millis":58,"errors":[],"result_count":0,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AMiSTer-devel%252FVIC20_MiSTer%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/sponsors/batch_deferred_sponsor_buttons":{"post":"FNxcWAj3vik65AiXPwxZm3MJKI29s_0RrvGG4IpEG69nj7Xn46Xyh-9vQNNRIXb0OC6L7jsTr8wbyTjcFmOcMw"}}},"title":"Repository search results"}