settings.py

# Set the Repository IP address and port
repository_ip = "localhost"
#repository_ip = "10.0.1.103"
repository_port = 8000


# Set the Application Manager websocket IP address and port
app_manager_ip = "localhost"
#app_manager_ip = "10.0.1.103"
app_manager_port = 8500


# Set the credentials for the Repository and Application Manager
repository_user = "miguel.costa@unparallel.pt"
repository_pass = "12345"


# Set the name of the User/Developer directory
repository_user_dir = "user"


# Set the name of the PT Code Analysis directory to get the Component Network
repository_pt_dir = "pt_code_analysis"
repository_descriptions_dir = "descriptions"


# Component Network Name
cn_name = "cn.xml"


# Set the target FPGA device - ZC706 = xc7z045ffg900-2
target_fpga = "xc7z045ffg900-2"