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dpu.hwh
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Mar 26 00:40:44 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynquplus" BOARD="em.avnet.com:ultra96v2:part0:1.0" DEVICE="xczu3eg" NAME="design_1" PACKAGE="sbva484" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
<PORT DIR="I" NAME="BT_ctsn" SIGIS="undef" SIGNAME="External_Ports_BT_ctsn">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="emio_uart0_ctsn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="BT_rtsn" SIGIS="undef" SIGNAME="psu_emio_uart0_rtsn">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="emio_uart0_rtsn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ENC_A" SIGIS="undef" SIGNAME="External_Ports_ENC_A">
<CONNECTIONS>
<CONNECTION INSTANCE="Angle_Encoder" PORT="A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ENC_B" SIGIS="undef" SIGNAME="External_Ports_ENC_B">
<CONNECTIONS>
<CONNECTION INSTANCE="Angle_Encoder" PORT="B"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ENC_I" SIGIS="undef" SIGNAME="External_Ports_ENC_I">
<CONNECTIONS>
<CONNECTION INSTANCE="Angle_Encoder" PORT="I"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="GH" RIGHT="0" SIGIS="undef" SIGNAME="PWM_pwm_h">
<CONNECTIONS>
<CONNECTION INSTANCE="PWM" PORT="pwm_h"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="GL" RIGHT="0" SIGIS="undef" SIGNAME="PWM_pwm_l">
<CONNECTIONS>
<CONNECTION INSTANCE="PWM" PORT="pwm_l"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="SCLK" SIGIS="undef" SIGNAME="ADC_Interface_clkout">
<CONNECTIONS>
<CONNECTION INSTANCE="ADC_Interface" PORT="clkout"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="SDI1" SIGIS="undef" SIGNAME="External_Ports_SDI1">
<CONNECTIONS>
<CONNECTION INSTANCE="xlconcat_0" PORT="In0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="SDI2" SIGIS="undef" SIGNAME="External_Ports_SDI2">
<CONNECTIONS>
<CONNECTION INSTANCE="xlconcat_0" PORT="In1"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="SDI3" SIGIS="undef" SIGNAME="External_Ports_SDI3">
<CONNECTIONS>
<CONNECTION INSTANCE="xlconcat_0" PORT="In2"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="SDV" SIGIS="undef" SIGNAME="External_Ports_SDV">
<CONNECTIONS>
<CONNECTION INSTANCE="xlconcat_0" PORT="In3"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="GPIO_0_tri_i" RIGHT="0" SIGIS="undef" SIGNAME="psu_emio_gpio_i">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="emio_gpio_i"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="GPIO_0_tri_o" RIGHT="0" SIGIS="undef" SIGNAME="psu_emio_gpio_o">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="emio_gpio_o"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="GPIO_0_tri_t" RIGHT="0" SIGIS="undef" SIGNAME="psu_emio_gpio_t">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="emio_gpio_t"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
<BUSINTERFACE BUSNAME="psu_GPIO_0" NAME="GPIO_0" TYPE="INITIATOR">
<PORTMAPS>
<PORTMAP LOGICAL="TRI_I" PHYSICAL="GPIO_0_tri_i"/>
<PORTMAP LOGICAL="TRI_O" PHYSICAL="GPIO_0_tri_o"/>
<PORTMAP LOGICAL="TRI_T" PHYSICAL="GPIO_0_tri_t"/>
</PORTMAPS>
</BUSINTERFACE>
</EXTERNALINTERFACES>
<MODULES>
<MODULE COREREVISION="27" FULLNAME="/ADC_Interface" HWVERSION="1.1" INSTANCE="ADC_Interface" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_AD7403" VLNV="trenz.biz:user:axis_AD7403:1.1">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="C_DECIMATION" VALUE="128"/>
<PARAMETER NAME="C_IMPLEMENTATION" VALUE="0"/>
<PARAMETER NAME="C_CLOCK_RATIO" VALUE="5"/>
<PARAMETER NAME="C_CHANNELS" VALUE="4"/>
<PARAMETER NAME="C_M_AXIS_TDEST_WIDTH" VALUE="2"/>
<PARAMETER NAME="C_M_AXIS_TDATA_WIDTH" VALUE="64"/>
<PARAMETER NAME="C_OUT_TYPE" VALUE="1"/>
<PARAMETER NAME="C_DATA_BITS" VALUE="16"/>
<PARAMETER NAME="C_SIGNED" VALUE="true"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_ADC_Interface_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT DIR="I" LEFT="3" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_0_dout">
<CONNECTIONS>
<CONNECTION INSTANCE="xlconcat_0" PORT="dout"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="clkout" SIGIS="undef" SIGNAME="ADC_Interface_clkout">
<CONNECTIONS>
<CONNECTION INSTANCE="External_Ports" PORT="SCLK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="update" SIGIS="undef"/>
<PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="ADC_Interface_m_axis_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_data_fifo_0" PORT="s_axis_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="ADC_Interface_m_axis_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_data_fifo_0" PORT="s_axis_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="ADC_Interface_m_axis_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_data_fifo_0" PORT="s_axis_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="clk_mux_0_clkout">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_mux_0" PORT="clkout"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_3_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="proc_sys_reset_3" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ADC_Interface_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="WIZ_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="12" FULLNAME="/AXI_StreamCapture_0" HWVERSION="1.0" INSTANCE="AXI_StreamCapture_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="AXI_StreamCapture" VLNV="trenz.biz:user:AXI_StreamCapture:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="" INTERFACE="S_AXI" NAME="S_AXI_reg" RANGE="4096" USAGE="register"/>
</ADDRESSBLOCKS>
<PARAMETERS>
<PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="5"/>
<PARAMETER NAME="C_BLOCK_SIZE" VALUE="8192"/>
<PARAMETER NAME="C_USE_TRIG" VALUE="FALSE"/>
<PARAMETER NAME="C_DATA_SYNC_TRIG" VALUE="FALSE"/>
<PARAMETER NAME="C_PRETRIG" VALUE="FALSE"/>
<PARAMETER NAME="C_S_AXIS_DATA_WIDTH" VALUE="64"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_AXI_StreamCapture_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
<PARAMETER NAME="C_S_AXI_BASEADDR" VALUE="0xB0000000"/>
<PARAMETER NAME="C_S_AXI_HIGHADDR" VALUE="0xB000FFFF"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="axi_aclk" SIGIS="clk" SIGNAME="psu_pl_clk0">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="pl_clk0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="dbg_fifo" PORT="m_axis_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="dbg_fifo" PORT="m_axis_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="dbg_fifo" PORT="m_axis_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="m_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="63" NAME="m_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="m_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_tkeep">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_tkeep"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="m_axis_s2mm_tlast" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_tlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="m_axis_s2mm_tready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="m_axis_s2mm_cmd_tvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_cmd_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_cmd_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="71" NAME="m_axis_s2mm_cmd_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_cmd_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_cmd_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="m_axis_s2mm_cmd_tready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_m_axis_s2mm_cmd_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="s_axis_s2mm_cmd_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axis_s2mm_sts_tready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_s2mm_sts_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="m_axis_s2mm_sts_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_sts_tdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_s2mm_sts_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="m_axis_s2mm_sts_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="s_axis_s2mm_sts_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_s2mm_sts_tkeep">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="m_axis_s2mm_sts_tkeep"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axis_s2mm_sts_tlast" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_s2mm_sts_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="m_axis_s2mm_sts_tlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axis_s2mm_sts_tvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axis_s2mm_sts_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_datamover_0" PORT="m_axis_s2mm_sts_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="AXI_StreamCapture_0_s_axi_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rready"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="WIZ_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="WIZ_NUM_REG" VALUE="8"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="5"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="0"/>
<PARAMETER NAME="HAS_LOCK" VALUE="0"/>
<PARAMETER NAME="HAS_PROT" VALUE="1"/>
<PARAMETER NAME="HAS_CACHE" VALUE="0"/>
<PARAMETER NAME="HAS_QOS" VALUE="0"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="AXI_StreamCapture_0_m_axis_s2mm" NAME="m_axis_s2mm" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_s2mm_tdata"/>
<PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_s2mm_tkeep"/>
<PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_s2mm_tlast"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_s2mm_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_s2mm_tready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="AXI_StreamCapture_0_m_axis_s2mm_cmd" NAME="m_axis_s2mm_cmd" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="9"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_s2mm_cmd_tdata"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_s2mm_cmd_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_s2mm_cmd_tready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="dbg_fifo_M_AXIS" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="axi_datamover_0_M_AXIS_S2MM_STS" NAME="s_axis_s2mm_sts" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_sts_tdata"/>
<PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_sts_tkeep"/>
<PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_sts_tlast"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_sts_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_sts_tready"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="39" FULLNAME="/Angle_Encoder" HWVERSION="1.0" INSTANCE="Angle_Encoder" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_encoder" VLNV="trenz.biz:user:axis_encoder:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="C_M_AXIS_TDATA_WIDTH" VALUE="16"/>
<PARAMETER NAME="C_FILTER_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_CPR" VALUE="1000"/>
<PARAMETER NAME="C_OUT_PERIOD" VALUE="64"/>
<PARAMETER NAME="C_ANGLE_AXIS" VALUE="true"/>
<PARAMETER NAME="C_PERIOD_AXIS" VALUE="FALSE"/>
<PARAMETER NAME="C_RPM_AXIS" VALUE="true"/>
<PARAMETER NAME="C_USE_SHIFT" VALUE="FALSE"/>
<PARAMETER NAME="C_INVERS_DIR" VALUE="FALSE"/>
<PARAMETER NAME="C_CLK_FREQ" VALUE="100000000"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_Angle_Encoder_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT DIR="I" NAME="A" SIGIS="undef" SIGNAME="External_Ports_ENC_A">
<CONNECTIONS>
<CONNECTION INSTANCE="External_Ports" PORT="ENC_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="B" SIGIS="undef" SIGNAME="External_Ports_ENC_B">
<CONNECTIONS>
<CONNECTION INSTANCE="External_Ports" PORT="ENC_B"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="I" SIGIS="undef" SIGNAME="External_Ports_ENC_I">
<CONNECTIONS>
<CONNECTION INSTANCE="External_Ports" PORT="ENC_I"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="angle_data" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" LEFT="15" NAME="period_data" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" LEFT="15" NAME="rpm_data" RIGHT="0" SIGIS="undef"/>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="axis_aclk" SIGIS="clk" SIGNAME="psu_pl_clk0">
<CONNECTIONS>
<CONNECTION INSTANCE="psu" PORT="pl_clk0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="m_angle_tvalid" SIGIS="undef" SIGNAME="Angle_Encoder_m_angle_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_concat_0" PORT="sc_axis_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="m_angle_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Angle_Encoder_m_angle_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_concat_0" PORT="sc_axis_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="m_angle_tready" SIGIS="undef" SIGNAME="Angle_Encoder_m_angle_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_concat_0" PORT="sc_axis_tready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="m_rpm_tvalid" SIGIS="undef" SIGNAME="Angle_Encoder_m_rpm_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_concat_0" PORT="sb_axis_tvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="m_rpm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Angle_Encoder_m_rpm_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_concat_0" PORT="sb_axis_tdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="m_rpm_tready" SIGIS="undef" SIGNAME="Angle_Encoder_m_rpm_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_concat_0" PORT="sb_axis_tready"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="Angle_Encoder_m_rpm" NAME="m_rpm" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TVALID" PHYSICAL="m_rpm_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="m_rpm_tready"/>
<PORTMAP LOGICAL="TDATA" PHYSICAL="m_rpm_tdata"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="Angle_Encoder_m_angle" NAME="m_angle" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_psu_0_pl_clk0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TVALID" PHYSICAL="m_angle_tvalid"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="m_angle_tready"/>
<PORTMAP LOGICAL="TDATA" PHYSICAL="m_angle_tdata"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="0" FULLNAME="/DPUCZDX8G_1" HWVERSION="1.0" INSTANCE="DPUCZDX8G_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="DPUCZDX8G" VLNV="xilinx.com:RTLKernel:DPUCZDX8G:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="" INTERFACE="S_AXI_CONTROL" NAME="reg0" RANGE="4096" USAGE="register"/>
</ADDRESSBLOCKS>
<PARAMETERS>
<PARAMETER NAME="DSP48_VER" VALUE="DSP48E2"/>
<PARAMETER NAME="S_AXI_FREQ_MHZ" VALUE="300"/>
<PARAMETER NAME="M_AXI_FREQ_MHZ" VALUE="300"/>
<PARAMETER NAME="AWRLEN_BW" VALUE="8"/>
<PARAMETER NAME="AWRUSER_BW" VALUE="1"/>
<PARAMETER NAME="AWRLOCK_BW" VALUE="1"/>
<PARAMETER NAME="GP_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP0_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP1_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP2_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP3_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP_DATA_BW" VALUE="128"/>
<PARAMETER NAME="SYS_IP_VER" VALUE="0x00000033"/>
<PARAMETER NAME="SYS_IP_TYPE" VALUE="0x00000001"/>
<PARAMETER NAME="SIZE_REGMAP_SIZE" VALUE="0x0000006B"/>
<PARAMETER NAME="SYS_REGMAP_VER" VALUE="2"/>
<PARAMETER NAME="TIME_YEAR" VALUE="20"/>
<PARAMETER NAME="TIME_MONTH" VALUE="11"/>
<PARAMETER NAME="TIME_DAY" VALUE="2"/>
<PARAMETER NAME="TIME_HOUR" VALUE="15"/>
<PARAMETER NAME="TIME_QUARTER" VALUE="1"/>
<PARAMETER NAME="GIT_COMMIT_ID" VALUE="0x1542BE4"/>
<PARAMETER NAME="GIT_COMMIT_TIME" VALUE="2011021524"/>
<PARAMETER NAME="VER_IP_REV" VALUE="0x00000000"/>
<PARAMETER NAME="VER_TARGET" VALUE="0x141"/>
<PARAMETER NAME="ARCH_HP_BW" VALUE="3"/>
<PARAMETER NAME="ARCH_DATA_BW" VALUE="1"/>
<PARAMETER NAME="ARCH_IMG_BKGRP" VALUE="2"/>
<PARAMETER NAME="ARCH_PP" VALUE="8"/>
<PARAMETER NAME="ARCH_ICP" VALUE="10"/>
<PARAMETER NAME="ARCH_OCP" VALUE="10"/>
<PARAMETER NAME="RAM_DEPTH_MEAN" VALUE="1"/>
<PARAMETER NAME="RAM_DEPTH_BIAS" VALUE="3"/>
<PARAMETER NAME="RAM_DEPTH_WGT" VALUE="3"/>
<PARAMETER NAME="RAM_DEPTH_IMG" VALUE="3"/>
<PARAMETER NAME="UBANK_IMG_N" VALUE="0"/>
<PARAMETER NAME="UBANK_WGT_N" VALUE="0"/>
<PARAMETER NAME="UBANK_BIAS" VALUE="0"/>
<PARAMETER NAME="DBANK_IMG_N" VALUE="0"/>
<PARAMETER NAME="DBANK_WGT_N" VALUE="0"/>
<PARAMETER NAME="DBANK_BIAS" VALUE="0"/>
<PARAMETER NAME="LOAD_AUGM" VALUE="0"/>
<PARAMETER NAME="LOAD_IMG_MEAN" VALUE="0"/>
<PARAMETER NAME="LOAD_PARALLEL" VALUE="2"/>
<PARAMETER NAME="CONV_LEAKYRELU" VALUE="1"/>
<PARAMETER NAME="CONV_RELU6" VALUE="1"/>
<PARAMETER NAME="CONV_WR_PARALLEL" VALUE="1"/>
<PARAMETER NAME="CONV_DSP_CASC_MAX" VALUE="4"/>
<PARAMETER NAME="CONV_DSP_ACCU_ENA" VALUE="1"/>
<PARAMETER NAME="SAVE_PARALLEL" VALUE="2"/>
<PARAMETER NAME="POOL_AVERAGE" VALUE="1"/>
<PARAMETER NAME="ELEW_MULT_EN" VALUE="0"/>
<PARAMETER NAME="ELEW_PARALLEL" VALUE="1"/>
<PARAMETER NAME="DWCV_ALU_MODE" VALUE="0"/>
<PARAMETER NAME="DWCV_RELU6" VALUE="1"/>
<PARAMETER NAME="DWCV_PARALLEL" VALUE="4"/>
<PARAMETER NAME="MISC_WR_PARALLEL" VALUE="1"/>
<PARAMETER NAME="DNNDK_PRINT" VALUE="xrt test"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_DPUCZDX8G_1_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
<PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
<PARAMETER NAME="C_HIGHADDR" VALUE="0x8000FFFF"/>
</PARAMETERS>
<PORTS>
<PORT DIR="O" LEFT="39" NAME="M_AXI_GP0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_GP0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_arlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_arready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_arvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="39" NAME="M_AXI_GP0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_GP0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_awlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_awready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_awvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_bready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_bvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="M_AXI_GP0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_rlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_rready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_rvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_wlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_wready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_wvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP0_FPD" PORT="S00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_aruser" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_awuser" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" LEFT="39" NAME="M_AXI_HP0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_HP0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_HP0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP0_arlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_arready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_arvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="39" NAME="M_AXI_HP0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_HP0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_HP0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP0_awlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_awready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_awvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_bready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_HP0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_bvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="127" NAME="M_AXI_HP0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_rlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_psu_S_AXI_HP1_FPD" PORT="S00_AXI_rlast"/>
</CONNECTIONS>
</PORT>