ADC function

[elhaouati]

Hi there,

I'm currently working on signal processing application, and I am relying on the ADC-DAC-DMA example. I am particularly interested in the ADC and the samples it sends. For a signal coming from a voltage generator that is externally synchronized using the clock output of the board, at a frequency of 62.5 = 250/4 MHz, I expect it to send the same or approximately the same 4 samples every period on the adc0[15:0] output of the block adc_dac, and does adc0[15:2] respect the conversion table in page 22 of the adc_datasheet

Is my understanding of the ADC function correct ?

Thank you in advance.

[jeanminet]

Hello,
Your understanding is correct.
The ADC in configured in two's complement format (https://github.com/Koheron/koheron-sdk/blob/master/boards/alpha250/drivers/ltc2157.hpp#L65).
adc0[15:2] = 10 0000 0000 0000 corresponds to about -0.5 V (1 Vpp ADC range)
adc0[15:2] = 01 1111 1111 1111 corresponds to about +0.5 V

Here is the Python code that convert the two complement representation of adc0[15:0] in an integer between -2^15 and 2^15:
https://github.com/Koheron/koheron-sdk/blob/master/examples/alpha250/adc-dac-dma/test.py#L46

[elhaouati]

Hello,
Thank you for your response.
In the ADC-DAC-DMA example, the ADC sampling rate is 250 Msps, and the clock output of the ZYNQ-7 Processing System is at 143 MHz. This means that we are processing these samples at a frequency lower than the rate at which they arrive. Is this situation going to cause us some problems or limitations in our system.

[jeanminet]

I don't know about your system but I can tell that no samples are lost in the process.
The datawidth of the S_AXI_HP0 port that sends data to the RAM is 64 bits.
64 bits x 143 MHz >> 16 bits x 250 MHz.