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DAC sampling rate #574

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Mohammed-678 opened this issue Jul 13, 2023 · 4 comments
Open

DAC sampling rate #574

Mohammed-678 opened this issue Jul 13, 2023 · 4 comments

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@Mohammed-678
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Hi
I tried to generate a signal at 62.5 MHz frequency and since the dac sampling rate is 250 MHz, I sent 4 samples (to devide the sampling frenquency by 4) on the DAC output I get 50 MHz signal rather than the 62.5 MHz expected. In the ZYNQ7 Processing System, I set my frequency to 250 MHz.

@tvanderbruggen
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Hi,

I suppose the signal is a sine wave.
How do you measure the 50 MHz: on an oscilloscope or by FFT ?
Because of the low number of samples per period, measurements vs time on a scope can be tricky ...

@Mohammed-678
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Mohammed-678 commented Jul 13, 2023

Yeah the signal is a sine wave.
I used them both and they both indicate 50 MHz, I am using the adc-dac-dma example.

@Mohammed-678
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Mohammed-678 commented Jul 17, 2023

I took the adc-dac-dma block design and i removed the phaselock Block then I sent a sample every clock period (my signal contain 4 samples) to the dac0 input of the block adc-dac.

@tvanderbruggen
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tvanderbruggen commented Jul 17, 2023

I'm not sure to understand, unless I missed something, there is no phaselock block in the adc-dac-dma design ...

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