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DAC sampling rate #574
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Hi, I suppose the signal is a sine wave. |
Yeah the signal is a sine wave. |
I took the adc-dac-dma block design and i removed the phaselock Block then I sent a sample every clock period (my signal contain 4 samples) to the dac0 input of the block adc-dac. |
I'm not sure to understand, unless I missed something, there is no phaselock block in the adc-dac-dma design ... |
Hi
I tried to generate a signal at 62.5 MHz frequency and since the dac sampling rate is 250 MHz, I sent 4 samples (to devide the sampling frenquency by 4) on the DAC output I get 50 MHz signal rather than the 62.5 MHz expected. In the ZYNQ7 Processing System, I set my frequency to 250 MHz.
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