From 82b732635f1adf5dd0b04b9290b589c1fc091f29 Mon Sep 17 00:00:00 2001
From: thomas <th.vanderbruggen@gmail.com>
Date: Wed, 9 Jun 2021 20:50:21 +0200
Subject: [PATCH] Add  variable to tcl scripts

---
 examples/alpha250/phase-noise-analyzer/block_design.tcl | 2 +-
 fpga/fpga.mk                                            | 4 ++--
 fpga/vivado/block_design.tcl                            | 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/examples/alpha250/phase-noise-analyzer/block_design.tcl b/examples/alpha250/phase-noise-analyzer/block_design.tcl
index 781aca5cc..6c9f0ed67 100644
--- a/examples/alpha250/phase-noise-analyzer/block_design.tcl
+++ b/examples/alpha250/phase-noise-analyzer/block_design.tcl
@@ -92,7 +92,7 @@ cell xilinx.com:ip:cic_compiler:4.0 cic {
   s_axis_data_tvalid [get_constant_pin 1 1]
 }
 
-set fir_coeffs [exec python $project_path/fir.py $n_stages $dec_rate $diff_delay print]
+set fir_coeffs [exec $python $project_path/fir.py $n_stages $dec_rate $diff_delay print]
 
 cell xilinx.com:ip:fir_compiler:7.2 fir {
   Filter_Type Decimation
diff --git a/fpga/fpga.mk b/fpga/fpga.mk
index b67586802..0b5e9c446 100644
--- a/fpga/fpga.mk
+++ b/fpga/fpga.mk
@@ -46,7 +46,7 @@ xpr: $(TMP_FPGA_PATH)/$(NAME).xpr
 
 $(TMP_FPGA_PATH)/$(NAME).xpr: $(CONFIG_TCL) $(XDC) $(PROJECT_PATH)/*.tcl $(CORES_COMPONENT_XML) | $(TMP_FPGA_PATH)
 	$(VIVADO_BATCH) -source $(FPGA_PATH)/vivado/project.tcl \
-	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc
+	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc $(PYTHON)
 	@echo [$@] OK
 
 .PHONY: fpga
@@ -64,7 +64,7 @@ $(TMP_FPGA_PATH)/$(NAME).hwdef: $(TMP_FPGA_PATH)/$(NAME).xpr | $(TMP_FPGA_PATH)
 .PHONY: block_design
 block_design: $(CONFIG_TCL) $(XDC) $(PROJECT_PATH)/*.tcl $(CORES_COMPONENT_XML)
 	$(VIVADO) -source $(FPGA_PATH)/vivado/block_design.tcl \
-	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc block_design_
+	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc $(PYTHON) block_design_
 
 # Open the Vivado project
 .PHONY: open_project
diff --git a/fpga/vivado/block_design.tcl b/fpga/vivado/block_design.tcl
index e35655249..602fd63ed 100644
--- a/fpga/vivado/block_design.tcl
+++ b/fpga/vivado/block_design.tcl
@@ -6,7 +6,8 @@ set board_path [lindex $argv 4]
 set mode [lindex $argv 5]
 set output_path [lindex $argv 6]
 set xdc_filename [lindex $argv 7]
-set prefix [lindex $argv 8]
+set python [lindex $argv 8]
+set prefix [lindex $argv 9]
 
 # Add optional prefix to the project name
 if {$prefix == "block_design_"} {