diff --git a/COMPONENT_CM4/TOOLCHAIN_ARM/linker.sct b/COMPONENT_CM4/TOOLCHAIN_ARM/linker.sct
index 9432312..98a97c3 100644
--- a/COMPONENT_CM4/TOOLCHAIN_ARM/linker.sct
+++ b/COMPONENT_CM4/TOOLCHAIN_ARM/linker.sct
@@ -65,7 +65,7 @@
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
+; https://github.com/Infineon/psoc6cm0p
; The size of the Cortex-M0+ application flash image
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x20000
diff --git a/COMPONENT_CM4/TOOLCHAIN_IAR/linker.icf b/COMPONENT_CM4/TOOLCHAIN_IAR/linker.icf
index 6262db3..468c397 100644
--- a/COMPONENT_CM4/TOOLCHAIN_IAR/linker.icf
+++ b/COMPONENT_CM4/TOOLCHAIN_IAR/linker.icf
@@ -130,7 +130,7 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
+ * https://github.com/Infineon/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x20000;
diff --git a/RELEASE.md b/RELEASE.md
index 328972a..57d6f79 100644
--- a/RELEASE.md
+++ b/RELEASE.md
@@ -15,6 +15,9 @@ The CY8CPROTO-063-BLE library includes the following:
* API documentation
### What Changed?
+#### v4.1.0
+* Add macro `CYBSP_USER_BTN_DRIVE` indicating the drive mode that should be used for user buttons
+* PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TFM.
#### v4.0.0
Note: This revision is only compatible with ModusToolbox Tools 3.0 and newer.
* Removed default dependency on CAPSENSE™ middleware. The library manager can be used to add this dependency if desired.
diff --git a/cybsp.c b/cybsp.c
index 4584c5c..33ae8af 100644
--- a/cybsp.c
+++ b/cybsp.c
@@ -115,7 +115,7 @@ cy_rslt_t cybsp_init(void)
// This is done to ensure configuration is available for all cores that might need to use it.
// In the case of a dual core project, this can be changed below to perform initialization on
// the CM4 if necessary.
- #if defined(CORE_NAME_CM0_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM4_0) && \
+ #if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM4_0) && \
defined(CY_USING_PREBUILT_CM0P_IMAGE))
cycfg_config_init();
#endif
diff --git a/cybsp.h b/cybsp.h
index 7740f18..cd27cf6 100644
--- a/cybsp.h
+++ b/cybsp.h
@@ -28,6 +28,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
+#include "cybsp_hw_config.h"
#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
#include "cybsp_bt_config.h"
#endif
diff --git a/cybsp_doc.h b/cybsp_doc.h
index 8445c71..1f9f0d6 100644
--- a/cybsp_doc.h
+++ b/cybsp_doc.h
@@ -23,8 +23,8 @@
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
-#if defined(COMPONENT_CAT4) /* CAT4 does not have configurators so the BSP defines pins in a
- * non-generated header */
+/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
+#if defined(COMPONENT_CAT4) || defined(COMPONENT_CAT5)
#include "cybsp_pins.h"
#else
#include "cycfg.h"
diff --git a/cybsp_hw_config.h b/cybsp_hw_config.h
new file mode 100644
index 0000000..580d49c
--- /dev/null
+++ b/cybsp_hw_config.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************//**
+ * \file cybsp_hw_config.h
+ *
+ * \brief
+ * Basic API for handling defaults for hardware so code examples behave the same across different
+ * devices.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef CYBSP_USER_BTN_DRIVE
+#define CYBSP_USER_BTN_DRIVE (CYHAL_GPIO_DRIVE_PULLUP)
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/props.json b/props.json
index f5c7b62..5863446 100644
--- a/props.json
+++ b/props.json
@@ -1,6 +1,6 @@
{
"core": {
- "version": "4.0.0.29660"
+ "version": "4.1.0.30528"
},
"opt": {
"props": {
diff --git a/system_psoc6.h b/system_psoc6.h
index eb65a16..259f015 100644
--- a/system_psoc6.h
+++ b/system_psoc6.h
@@ -69,7 +69,7 @@
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
+* https://github.com/Infineon/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
@@ -106,7 +106,7 @@
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
+* https://github.com/Infineon/psoc6cm0p
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
@@ -156,7 +156,7 @@
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
+* https://github.com/Infineon/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
@@ -240,7 +240,7 @@
* clib-support library that provides newlib-compatible implementations of
* 'sbrk', '__malloc_lock' and '__malloc_unlock':
*
-* https://github.com/cypresssemiconductorco/clib-support.
+* https://github.com/Infineon/clib-support.
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
* - Editing source code files\n