diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index e6f020c..6811fdf 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 2e1d84b..b4e30e0 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 216bafa..4114cb1 100755 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,8 +4,8 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 0d31cfa..a00457a 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index e712b85..e9c0ef8 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 39bf8ec..b25adc8 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 7badcb5..591d07e 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 97674bc..e212686 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -53,6 +53,9 @@ extern "C" { #if defined (CY_USING_HAL) #define WCO_IN_HAL_PORT_PIN P0_0 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_IN P0_0 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -77,6 +80,9 @@ extern "C" { #if defined (CY_USING_HAL) #define WCO_OUT_HAL_PORT_PIN P0_1 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_OUT P0_1 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -101,6 +107,9 @@ extern "C" { #if defined (CY_USING_HAL) #define SWDIO_HAL_PORT_PIN P6_6 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWDIO P6_6 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -125,6 +134,9 @@ extern "C" { #if defined (CY_USING_HAL) #define SWCLK_HAL_PORT_PIN P6_7 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWCLK P6_7 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index 7195301..9de76f9 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index add7b12..d7955be 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 9a92b14..749c8da 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -32,47 +32,80 @@ #define CY_CFG_SYSCLK_FLL_ERROR 4 #define CY_CFG_SYSCLK_WCO_ERROR 5 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 #define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_MULT 500U +#define CY_CFG_SYSCLK_FLL_REFDIV 20U +#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4 +#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true +#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U +#define CY_CFG_SYSCLK_FLL_IGAIN 9U +#define CY_CFG_SYSCLK_FLL_PGAIN 5U +#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8 +#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT +#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355 +#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 #define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_ILO_HIBERNATE true #define CY_CFG_SYSCLK_IMO_ENABLED 1 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 1 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 #define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_IN_PIN 0U +#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U +#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED #define CY_CFG_PWR_ENABLED 1 #define CY_CFG_PWR_INIT 1 #define CY_CFG_PWR_USING_PMIC 0 #define CY_CFG_PWR_VBACKUP_USING_VDDD 1 #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 +#define CY_CFG_PWR_REGULATOR_MODE_MIN false -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = -{ - .fllMult = 500U, - .refDiv = 20U, - .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, - .enableOutputDiv = true, - .lockTolerance = 10U, - .igain = 9U, - .pgain = 5U, - .settlingCount = 8U, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, - .cco_Freq = 355U, -}; +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig; +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = + { + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if defined (CY_USING_HAL) const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { @@ -119,393 +152,946 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) (void)error; /* Suppress the compiler warning */ while(1); } -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_FllInit() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath2Init() -{ - Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath3Init() -{ - Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath4Init() -{ - Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(1U); -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_WcoInit() -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -__STATIC_INLINE void init_cycfg_power(void) -{ - /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ - #if (CY_CFG_PWR_VBACKUP_USING_VDDD) - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } - #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ - #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - - /* Configure core regulator */ - #if CY_CFG_PWR_USING_LDO - Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); - #else - Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - #endif /* CY_CFG_PWR_USING_LDO */ - /* Configure PMIC */ - Cy_SysPm_UnlockPmic(); - #if CY_CFG_PWR_USING_PMIC - Cy_SysPm_PmicEnableOutput(); - #else - Cy_SysPm_PmicDisableOutput(); - #endif /* CY_CFG_PWR_USING_PMIC */ -} +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + __STATIC_INLINE void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config) + { + #ifdef CY_CFG_PWR_ENABLED + secure_config->powerEnable = CY_CFG_PWR_ENABLED; + #endif /* CY_CFG_PWR_ENABLED */ + #ifdef CY_CFG_PWR_USING_LDO + secure_config->ldoEnable = CY_CFG_PWR_USING_LDO; + #endif /* CY_CFG_PWR_USING_LDO */ -void init_cycfg_system(void) -{ - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); - #ifdef CY_CFG_PWR_ENABLED - #ifdef CY_CFG_PWR_INIT - init_cycfg_power(); - #else - #warning Power system will not be configured. Update power personality to v1.20 or later. - #endif /* CY_CFG_PWR_INIT */ - #endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + #ifdef CY_CFG_PWR_USING_PMIC + secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC; + #endif /* CY_CFG_PWR_USING_PMIC */ + + #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD + secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD; + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + #ifdef CY_CFG_PWR_USING_ULP + secure_config->ulpEnable = CY_CFG_PWR_USING_ULP; + #endif /* CY_CFG_PWR_USING_ULP */ + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED; + #endif /* CY_CFG_SYSCLK_ECO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED; + #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED; + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED; + #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED; + #endif /* CY_CFG_SYSCLK_FLL_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED + secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED; + #endif /* CY_CFG_SYSCLK_PILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED; + #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */ + + #ifdef CY_CFG_PWR_LDO_VOLTAGE + secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE; + #endif /* CY_CFG_PWR_LDO_VOLTAGE */ + + #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN + secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN; + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + + #ifdef CY_CFG_PWR_BUCK_VOLTAGE + secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE; + #endif /* CY_CFG_PWR_BUCK_VOLTAGE */ + + #ifdef CY_CFG_SYSCLK_ECO_FREQ + secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ECO_CLOAD + secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ECO_ESR + secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR; + #endif /* CY_CFG_SYSCLK_ECO_ESR */ + + #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL + secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL; + #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT + secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT + secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN + secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN + secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ; + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT + secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN + secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM + secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */ + + #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE + secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE; + #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */ + + #ifdef CY_CFG_SYSCLK_WCO_BYPASS + secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS; + #endif /* CY_CFG_SYSCLK_WCO_BYPASS */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PRT + secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT; + #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT + secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PIN + secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN; + #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN + secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ + secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_FLL_MULT + secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT; + #endif /* CY_CFG_SYSCLK_FLL_MULT */ + + #ifdef CY_CFG_SYSCLK_FLL_REFDIV + secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV; + #endif /* CY_CFG_SYSCLK_FLL_REFDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE + secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE; + #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV + secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV; + #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE + secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE; + #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */ + + #ifdef CY_CFG_SYSCLK_FLL_IGAIN + secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN; + #endif /* CY_CFG_SYSCLK_FLL_IGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_PGAIN + secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN; + #endif /* CY_CFG_SYSCLK_FLL_PGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT + secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT; + #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */ + + #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE + secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ + secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV + secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV + secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV + secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE + secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE + secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ + secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV + secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV + secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV + secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE + secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE + secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ + secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE + secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE + secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE + secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE + secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE + secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE + secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER + secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER + secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER + secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH + secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER + secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ + secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH + secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER + secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ + secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH + secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER + secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ + secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH + secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER + secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ + secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH + secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER + secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ + secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH + secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER + secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ + secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE + secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER + secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE + secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE + secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE + secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER + secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE + secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD + secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME + secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ + secure_config->altHFfreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV + secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR + secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */ + } +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkBakInit() { - (void)Cy_SysClk_PllDisable(pll); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkFastInit() + { + Cy_SysClk_ClkFastSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_FllInit() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf0Init() + { + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_IloInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkLfInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath0Init() + { + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath1Init() { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath2Init() + { + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath3Init() + { + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath4Init() + { + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPeriInit() + { + Cy_SysClk_ClkPeriSetDivider(1U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkSlowInit() + { + Cy_SysClk_ClkSlowSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_WcoInit() + { + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void init_cycfg_power(void) + { + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + /* Configure core regulator */ + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + #if CY_CFG_PWR_REGULATOR_MODE_MIN + Cy_SysPm_SystemSetMinRegulatorCurrent(); + #else + Cy_SysPm_SystemSetNormalRegulatorCurrent(); + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif +void init_cycfg_system(void) +{ + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_en_pra_status_t configStatus; + init_cycfg_secure_struct(&srss_0_clock_0_secureConfig); + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif - /* Enable all source clocks */ - #ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); - #endif + configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC, + CY_PRA_FUNC_INIT_CYCFG_DEVICE, + &srss_0_clock_0_secureConfig); + if ( configStatus != CY_PRA_STATUS_SUCCESS ) + { + cycfg_ClockStartupError(configStatus); + } - #ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); - #endif + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ); + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + #else /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ - #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); - #endif + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ - #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); - #endif + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - #ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); - #endif + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } - #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); - #endif + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif - /* Configure CPU clock dividers */ - #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); - #endif + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif - #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); - #endif + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); - #else - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); #endif - #endif - /* Configure Path Clocks */ - #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); - #endif + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif - /* Configure and enable FLL */ - #ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); - #endif + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif - Cy_SysClk_ClkHf0Init(); + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); #endif - #endif - /* Configure and enable PLLs */ - #ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); - #endif + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif - /* Configure HF clocks */ - #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); - #endif + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif - /* Configure miscellaneous clocks */ - #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); - #endif + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif - #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); - #endif + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif - #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); - #endif + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif - #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); - #endif + Cy_SysClk_ClkHf0Init(); - /* Configure default enabled clocks */ - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); - #else - Cy_SysClk_IloDisable(); - Cy_SysClk_IloHibernateOn(false); - #endif + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif - #ifndef CY_CFG_SYSCLK_IMO_ENABLED - #error the IMO must be enabled for proper chip operation - #endif + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ #ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); + Cy_SysClk_MfoInit(); #endif #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); + Cy_SysClk_ClkMfInit(); #endif - /* Set accurate flash wait states */ - #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); - #endif + #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + #ifndef CY_CFG_SYSCLK_ILO_ENABLED + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */ + Cy_SysLib_DelayUs(200U); + #endif + Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); + #endif + + #endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */ - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 6db989a..a7dc76a 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -29,6 +29,8 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" +#include "cy_pra.h" +#include "cy_pra_cfg.h" #include "cy_ble_clk.h" #if defined (CY_USING_HAL) #include "cyhal_hwmgr.h" @@ -47,10 +49,12 @@ extern "C" { #define srss_0_clock_0_fll_0_ENABLED 1U #define srss_0_clock_0_hfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF0 0UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U #define srss_0_clock_0_pathmux_2_ENABLED 1U diff --git a/COMPONENT_BSP_DESIGN_MODUS/design.modus b/COMPONENT_BSP_DESIGN_MODUS/design.modus index d648858..31be9bb 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -155,7 +155,7 @@ - + diff --git a/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 3c70be4..d573d95 100644 --- a/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70.1 +;* \version 2.80 ;* ;* Linker file for the ARMCC. ;* diff --git a/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index 1e40f15..ed628a9 100644 --- a/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70.1 +* \version 2.80 * * Linker file for the GNU C compiler. * diff --git a/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3934087..412fc76 100644 --- a/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70.1 +* \version 2.80 * * Linker file for the IAR compiler. * diff --git a/COMPONENT_CM0P/system_psoc6_cm0plus.c b/COMPONENT_CM0P/system_psoc6_cm0plus.c index 5f2d588..e3080a5 100644 --- a/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70.1 +* \version 2.80 * * The device system-source file. * @@ -130,6 +130,7 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * * - Unlocks and disables WDT. * - Calls Cy_PDL_Init() function to define the driver library. * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. * - Calls \ref SystemCoreClockUpdate(). * *******************************************************************************/ diff --git a/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index e515fb3..7da451c 100644 --- a/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70.1 +;* \version 2.80 ;* ;* Linker file for the ARMCC. ;* diff --git a/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk b/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk index 20b0085..f8fd2ed 100644 --- a/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk +++ b/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx7_cm4_dual.mk -# \version 2.70.1 +# \version 2.80 # # \brief # Specifies the starting address and the size of the segments in the output diff --git a/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 39b4f82..574bcd0 100644 --- a/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70.1 +* \version 2.80 * * Linker file for the GNU C compiler. * diff --git a/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index bb93cf4..1e644dd 100644 --- a/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70.1 +* \version 2.80 * * Linker file for the IAR compiler. * diff --git a/COMPONENT_CM4/system_psoc6_cm4.c b/COMPONENT_CM4/system_psoc6_cm4.c index 4260fab..d717147 100644 --- a/COMPONENT_CM4/system_psoc6_cm4.c +++ b/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70.1 +* \version 2.80 * * The device system-source file. * @@ -40,6 +40,10 @@ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + /******************************************************************************* * SystemCoreClockUpdate() @@ -125,6 +129,7 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * * - Unlocks and disables WDT. * - Calls Cy_PDL_Init() function to define the driver library. * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref Cy_PRA_Init() for PSoC 64 devices. * - Calls \ref SystemCoreClockUpdate(). * \endcond *******************************************************************************/ @@ -233,6 +238,11 @@ void SystemInit(void) #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + /* Initialize Protected Register Access driver */ + Cy_PRA_Init(); +#endif /* defined(CY_DEVICE_SECURE) */ } diff --git a/README.md b/README.md index a1ee778..46b6494 100644 --- a/README.md +++ b/README.md @@ -3,6 +3,7 @@ ## Overview The PSoC 6 BLE Prototyping Kit (CY8CPROTO-063-BLE) is a low-cost hardware platform that enables design and debug of PSoC 6 MCUs. This kit is designed with a snap-away form-factor, allowing users to separate the KitProg (on-board programmer and debugger) from the target board and use independently. + ![](docs/html/board.png) To use code from the BSP, simply include a reference to `cybsp.h`. @@ -27,17 +28,18 @@ The BSP has a few hooks that allow its behavior to be configured. Some of these Components: * Device specific HAL reference (e.g.: PSOC6HAL) - This component, enabled by default, pulls in the version of the HAL that is applicable for this board. - * CYBSP_WIFI_CAPABLE - This component, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip. * BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component. * CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component. Defines: + * CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip. * CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers. ### Clock Configuration | Clock | Source | Output Frequency | |----------|-----------|------------------| +| FLL | IMO | 100.0 MHz | | CLK_HF0 | CLK_PATH0 | 100 MHz | ### Power Configuration @@ -56,7 +58,7 @@ See the [BSP API Reference Manual][api] for the complete list of the provided in ## More information * [CY8CPROTO-063-BLE BSP API Reference Manual][api] * [CY8CPROTO-063-BLE Documentation](http://www.cypress.com/CY8CPROTO-063-BLE) -* [Cypress Semiconductor](http://www.cypress.com) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) * [Cypress Semiconductor GitHub](https://github.com/cypresssemiconductorco) * [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment) diff --git a/RELEASE.md b/RELEASE.md index 93403d7..9405864 100644 --- a/RELEASE.md +++ b/RELEASE.md @@ -15,14 +15,20 @@ The CY8CPROTO-063-BLE library includes the following: * API documentation ### What Changed? +#### v1.3.0 +* Minor update for documentation & branding +* Updated design files to use latest personality files +* Initialize VDDA voltage if set in configurator +NOTE: This requires psoc6hal 1.3.0 or later #### v1.2.1 -* Add 43012/4343W/43438 component to appropriate BSPs +* Added 43012/4343W/43438 component to appropriate BSPs * Added multi-image policy for secure (064) BSPs #### v1.2.0 * Standardize version numbering for all boards in a family * Moved UDB SDIO implementation into its own library udb-sdio-whd library * Added call to setup HAL SysPM driver (requires HAL 1.2.0 or later) * Updated documentation +NOTE: This requires psoc6hal 1.2.0 or later #### v1.1.0 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core specific directories. * Minor updates to avoid potential warnings on some toolchains @@ -44,7 +50,7 @@ This version of the CY8CPROTO-063-BLE BSP was validated for compatibility with t ### More information * [CY8CPROTO-063-BLE BSP API Reference Manual][api] * [CY8CPROTO-063-BLE Documentation](http://www.cypress.com/CY8CPROTO-063-BLE) -* [Cypress Semiconductor](http://www.cypress.com) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) * [Cypress Semiconductor GitHub](https://github.com/cypresssemiconductorco) * [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment) diff --git a/cybsp.c b/cybsp.c index acd73e3..4d49b35 100644 --- a/cybsp.c +++ b/cybsp.c @@ -87,6 +87,14 @@ cy_rslt_t cybsp_init(void) { result = cyhal_syspm_init(); } + +#ifdef CY_CFG_PWR_VDDA_MV + if(CY_RSLT_SUCCESS == result) + { + cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV); + } +#endif + #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif diff --git a/docs/html/cypress_logo.png b/docs/html/cypress_logo.png deleted file mode 100644 index ac9ba09..0000000 Binary files a/docs/html/cypress_logo.png and /dev/null differ diff --git a/docs/html/doxygen_style.css b/docs/html/doxygen_style.css index 84b29ec..b4893b1 100644 --- a/docs/html/doxygen_style.css +++ b/docs/html/doxygen_style.css @@ -1488,7 +1488,7 @@ tr.heading h2 { */ /* cypress logo */ -img[src="cypress_logo.png"]{ +img[src="logo.png"]{ height:75px; /*float: right;*/ } diff --git a/docs/html/group__group__bsp__functions.html b/docs/html/group__group__bsp__functions.html index 57f4517..4cf6c42 100644 --- a/docs/html/group__group__bsp__functions.html +++ b/docs/html/group__group__bsp__functions.html @@ -29,7 +29,7 @@ - + diff --git a/docs/html/group__group__bsp__macros.html b/docs/html/group__group__bsp__macros.html index 95a3a22..faeece8 100644 --- a/docs/html/group__group__bsp__macros.html +++ b/docs/html/group__group__bsp__macros.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/group__group__bsp__pin__state.html b/docs/html/group__group__bsp__pin__state.html index d573f0f..1bc9d33 100644 --- a/docs/html/group__group__bsp__pin__state.html +++ b/docs/html/group__group__bsp__pin__state.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/group__group__bsp__pins.html b/docs/html/group__group__bsp__pins.html index 7eca4c4..5ef1146 100644 --- a/docs/html/group__group__bsp__pins.html +++ b/docs/html/group__group__bsp__pins.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/group__group__bsp__pins__btn.html b/docs/html/group__group__bsp__pins__btn.html index 510efac..6bbbced 100644 --- a/docs/html/group__group__bsp__pins__btn.html +++ b/docs/html/group__group__bsp__pins__btn.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/group__group__bsp__pins__comm.html b/docs/html/group__group__bsp__pins__comm.html index e70af27..bd5908a 100644 --- a/docs/html/group__group__bsp__pins__comm.html +++ b/docs/html/group__group__bsp__pins__comm.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/group__group__bsp__pins__led.html b/docs/html/group__group__bsp__pins__led.html index fa51e42..9b5bda3 100644 --- a/docs/html/group__group__bsp__pins__led.html +++ b/docs/html/group__group__bsp__pins__led.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/group__group__bsp__settings.html b/docs/html/group__group__bsp__settings.html index 9532b01..04d09c1 100644 --- a/docs/html/group__group__bsp__settings.html +++ b/docs/html/group__group__bsp__settings.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/docs/html/index.html b/docs/html/index.html index 7182773..49a6b1d 100644 --- a/docs/html/index.html +++ b/docs/html/index.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + @@ -91,7 +91,8 @@

Overview

-

The PSoC 6 BLE Prototyping Kit (CY8CPROTO-063-BLE) is a low-cost hardware platform that enables design and debug of PSoC 6 MCUs. This kit is designed with a snap-away form-factor, allowing users to separate the KitProg (on-board programmer and debugger) from the target board and use independently.

+

The PSoC 6 BLE Prototyping Kit (CY8CPROTO-063-BLE) is a low-cost hardware platform that enables design and debug of PSoC 6 MCUs. This kit is designed with a snap-away form-factor, allowing users to separate the KitProg (on-board programmer and debugger) from the target board and use independently.

+
board.png

To use code from the BSP, simply include a reference to cybsp.h.

@@ -112,11 +113,11 @@

BSP Configuration

The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CPROTO-063-BLE.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.

Components:

  • Device specific HAL reference (e.g.: PSOC6HAL) - This component, enabled by default, pulls in the version of the HAL that is applicable for this board.
    • -
  • CYBSP_WIFI_CAPABLE - This component, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip.
  • BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component.
  • CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component.

Defines:

    +
  • CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip.
  • CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.

Clock Configuration

@@ -124,6 +125,8 @@

Clock Configuration

+ +
CY8CPROTO-063-BLE BSP
Clock Source Output Frequency
FLL IMO 100.0 MHz
CLK_HF0 CLK_PATH0 100 MHz

Power Configuration

@@ -140,7 +143,7 @@

More information

diff --git a/docs/html/logo.png b/docs/html/logo.png new file mode 100644 index 0000000..c6d2b8e Binary files /dev/null and b/docs/html/logo.png differ diff --git a/docs/html/md_bsp_boards_mt_bsp_user_guide.html b/docs/html/md_bsp_boards_mt_bsp_user_guide.html index ad66013..d58f29e 100644 --- a/docs/html/md_bsp_boards_mt_bsp_user_guide.html +++ b/docs/html/md_bsp_boards_mt_bsp_user_guide.html @@ -29,7 +29,7 @@ - + @@ -91,7 +91,7 @@

Introduction

-

A Board Support Package (BSP) provides a standard interface to a board's features and capabilities. The API is consistent across Cypress kits. Other software (such as middleware or the user's application) can use the BSP to configure and control the hardware. BSPs have the following characteristics:

+

A Board Support Package (BSP) provides a standard interface to a board's features and capabilities. The API is consistent across PSoC kits. Other software (such as middleware or the user's application) can use the BSP to configure and control the hardware. BSPs have the following characteristics:

  • BSPs initialize device resources, such as clocks and power supplies to set up the device to run firmware.
  • BSPs contain linker scripts and startup code so you can customize them for your board.
    • @@ -101,12 +101,12 @@

For a complete description of what the BSP provides and how it is used within ModusToolbox, see the ModusToolbox User Guide

Quick Start with BSPs

-

This section provides a high-level view for using BSPs. You should be familiar with creating an application using both the ModusToolbox IDE and command-line environments. To use a BSP for a Cypress kit you need to perform the following steps:

    +

    This section provides a high-level view for using BSPs. You should be familiar with creating an application using both the ModusToolbox IDE and command-line environments. To use a BSP for a kit you need to perform the following steps:

    1. Get a BSP using one of the following methods:
      • Create an application with the Project Creation tool included with the ModusToolbox software installer (< ModusToolbox install>/tools_2.x/project-creator). This tool can also be launched from the Eclipse IDE for ModusToolbox. The tool fetches the BSP for the kit that you selected, and places it in the libs directory.
      • In an existing application, use the Library Manager tool to fetch the required BSP. This tool is located in < ModusToolbox install >/tools_2.x/library-manager. You can also launch it from within the ModusToolbox IDE.
      • In an existing application, create a .lib file specifying the BSP and version (commit, tag, or branch). Then run make getlibs to fetch the BSP and any associated libraries. The .lib file typically goes in the deps directory.
        • -
      • In an existing application, clone the Cypress BSP GitHub repository using the git clone command. For example: git clone [https://github.com/cypresssemiconductorco/TARGET_CY8CPROTO-062-4343W/#latest-v1.X] A BSP includes other libraries. To fetch all the libraries, use the make getlibs command from a command shell in the top directory of the application.
        • +
      • In an existing application, clone the BSP GitHub repository using the git clone command. For example: git clone [https://github.com/cypresssemiconductorco/TARGET_CY8CPROTO-062-4343W/#latest-v1.X] A BSP includes other libraries. To fetch all the libraries, use the make getlibs command from a command shell in the top directory of the application.
    2. Add #include "cybsp.h" to your main.c file.
      3. @@ -117,7 +117,7 @@

      References

diff --git a/docs/html/modules.html b/docs/html/modules.html index 9d7ae85..45be78f 100644 --- a/docs/html/modules.html +++ b/docs/html/modules.html @@ -29,7 +29,7 @@
CY8CPROTO-063-BLE BSP
- + diff --git a/system_psoc6.h b/system_psoc6.h index 58550fa..867f26f 100644 --- a/system_psoc6.h +++ b/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70.1 +* \version 2.80 * * \brief Device system header file. * @@ -85,20 +85,20 @@ * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's -* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image -* of the Cortex-M0+ application should be the same value as the flash LENGTH in -* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. * Do this by either: * - Passing the following commands to the compiler:\n * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode * or -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where * 'xx' is the device family:\n * \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for * example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The @@ -135,9 +135,9 @@ * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image -* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the -* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. * Do this by either: * - Passing the following commands to the compiler:\n * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode @@ -175,11 +175,11 @@ * define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value -* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the * 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result -* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the * 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n * \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode @@ -212,8 +212,8 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is allocated -* dynamically to the whole available free memory up to stack memory and it +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it * is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC @@ -229,6 +229,19 @@ * Change the stack size by modifying the following line:\n * \code STACK_SIZE = 0x1000; \endcode * +* \note Correct operation of malloc and related functions depends on the working +* implementation of the 'sbrk' function. Newlib-nano (default C runtime library +* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that +* doesn't check for heap and stack collisions during excessive memory allocations. +* To ensure the heap always remains within the range defined by __HeapBase and +* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: +* \snippet startup/snippet/main.c snippet_sbrk +* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include +* clib-support library that provides newlib-compatible implementations of +* 'sbrk', '__malloc_lock' and '__malloc_unlock': +*
+* https://github.com/cypresssemiconductorco/clib-support. +* * \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n * The stack size is defined in the linker script files: 'xx_yy.sct', @@ -321,6 +334,16 @@ * * * +* +* +* +* +* +* +* +* +* * * * diff --git a/version.xml b/version.xml index 6ecc36b..f705023 100644 --- a/version.xml +++ b/version.xml @@ -1 +1 @@ -1.2.1.14103 +1.3.0.15346
CY8CPROTO-063-BLE BSP
Reason for Change
2.80Updated linker scripts for PSoC 64 Secure MCU devices.Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates +* in accordance with the PSoC 64 Secure Boot SDK policies.
Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.