diff --git a/COMPONENT_CM0P/system_psoc6_cm0plus.c b/COMPONENT_CM0P/system_psoc6_cm0plus.c index 2e2b152..5f2d588 100644 --- a/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -40,6 +40,10 @@ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + /******************************************************************************* * SystemCoreClockUpdate() @@ -219,6 +223,11 @@ void SystemInit(void) #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + #if defined(CY_DEVICE_SECURE) + /* Initialize Protected Regsiter Access driver. */ + Cy_PRA_Init(); + #endif /* defined(CY_DEVICE_SECURE) */ } @@ -263,7 +272,7 @@ void SystemCoreClockUpdate (void) cy_Hfclk0FreqHz = locHf0Clock; cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); - + /* Sets clock frequency for Delay API */ cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); diff --git a/COMPONENT_CM4/system_psoc6_cm4.c b/COMPONENT_CM4/system_psoc6_cm4.c index 7e634e2..4260fab 100644 --- a/COMPONENT_CM4/system_psoc6_cm4.c +++ b/COMPONENT_CM4/system_psoc6_cm4.c @@ -160,7 +160,7 @@ void SystemInit(void) #ifdef __CM0P_PRESENT #if (__CM0P_PRESENT == 0) /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << CY_STARTUP_IPC7_DP_OFFSET); /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ diff --git a/RELEASE.md b/RELEASE.md index b57048a..93403d7 100644 --- a/RELEASE.md +++ b/RELEASE.md @@ -15,6 +15,9 @@ The CY8CPROTO-063-BLE library includes the following: * API documentation ### What Changed? +#### v1.2.1 +* Add 43012/4343W/43438 component to appropriate BSPs +* Added multi-image policy for secure (064) BSPs #### v1.2.0 * Standardize version numbering for all boards in a family * Moved UDB SDIO implementation into its own library udb-sdio-whd library diff --git a/cybsp_types.h b/cybsp_types.h index 5f2a864..3ac784f 100644 --- a/cybsp_types.h +++ b/cybsp_types.h @@ -54,7 +54,7 @@ extern "C" { * | I2C | Role | Master | Configurable to slave mode through HAL function | * | ^ | Data rate | 100 kbps | Configurable through HAL function | * | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| +* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter; 1 count = 1/32768 second or 32768 counts = 1 second ||| * | SPI | Data rate | 100 kpbs | Configurable through HAL function | * | ^ | Slave select polarity | Active low | | * | UART | Flow control | No flow control | Configurable through HAL function | diff --git a/docs/html/group__group__bsp__settings.html b/docs/html/group__group__bsp__settings.html index 630be96..9532b01 100644 --- a/docs/html/group__group__bsp__settings.html +++ b/docs/html/group__group__bsp__settings.html @@ -115,9 +115,19 @@ Data rate 100 kbps Configurable through HAL function Drive mode of SCL & SDA pins Open Drain (drives low) External pull-up resistors are required + +LpTimer Uses WCO (32.768 kHz) as clock source & MCWDT as counter; 1 count = 1/32768 second or 32768 counts = 1 second + +SPI Data rate 100 kpbs Configurable through HAL function + +Slave select polarity Active low + +UART Flow control No flow control Configurable through HAL function + +Data format 8N1 Configurable through HAL function + +Baud rate 115200 Configurable through HAL function -

| LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter.

-

1 count = 1/32768 second or 32768 counts = 1 second. ||| | SPI | Data rate | 100 kpbs | Configurable through HAL function | | ^ | Slave select polarity | Active low | | | UART | Flow control | No flow control | Configurable through HAL function | | ^ | Data format | 8N1 | Configurable through HAL function | | ^ | Baud rate | 115200 | Configurable through HAL function |