Working with Combinational Designs

[PiyushSaini97]

Hi,

I was running the design c17.v in Benchmarks/ISCAS_85. However, while generating TV, the command requires me to add clock as well and obviously a combinational circuit does not have clock.

Verilog Code:

My question: Is it possible to generate TV and find faults for pure combinational designs?

[priyajit99]

Same issue . have u found any solution?? @donn can u pls reply how T.V 's were generated for comb ckts in the paper published on FAULT: An open source DFT Toolchain

[donn]

I think you can just pass --clock NULL. I can't recall why we requireclock at the moment, but I do recall it not being required in an earlier version.

[donn]

I'm not seeing any attachment. Can you please reply on GitHub?

[priyajit99]

It is showing this error

[donn]

Ugh... yeah, that tracks. Okay. I'll look into it.

[donn]

You may want to consider adding a dummy clock port that does nothing for now.

[donn]

Alright, so I've put in the research.

Fact is- combinational designs are a tiny minority of practical circuits. So, I've added instructions to the Wiki that just recommend adding a dummy clock and reset port to the design, which will be later used for the scan chain and JTAG TAP.

Sorry for the inconvenience. The alternative would again greatly complicate the codebase, at the cost of adding two unused inputs. It's not worth it.