verilog
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The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.
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Jun 2, 2024 - HTML
Verilator open-source SystemVerilog simulator and lint system
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Jun 2, 2024 - C++
Sol-1: A CPU/Computer System made from 74 series logic.
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Jun 2, 2024 - C
Basic implementation of SDRAM controller for De0-nano board.
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Jun 2, 2024 - Verilog
A package to generate Verilog/SystemVerilog code on Julia.
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Jun 2, 2024 - Julia
Python Templated Verilog
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Jun 2, 2024 - Rust
a verilog implementation of arbitrary waveform generator with Red Pitaya
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Jun 2, 2024 - Jupyter Notebook
learn the combinational and sequential logic circuit.
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Jun 2, 2024 - SystemVerilog
SystemVerilog compiler and language services
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Jun 2, 2024 - C++
Norsk Data ND-120 CPU Design Documents. Modern Logisim and HDL implementation
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Jun 1, 2024 - Verilog
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
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Jun 1, 2024 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jun 2, 2024 - Verilog
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