AutoSA: Polyhedral-Based Systolic Array Compiler
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Updated
Dec 8, 2022 - C++
AutoSA: Polyhedral-Based Systolic Array Compiler
Template for project1 TPU
Research and Materials on Hardware implementation of Transformer Model
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
AI acceleration using matrix multiplication with half the multiplications
A general framework for optimizing DNN dataflow on systolic array
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
Systolic-array based Deep Learning Accelerator generator
EE599 Accelerated Computing on FPGA
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
Systolic arrays graphical simulator (SAGS), written in Python.
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
SystemVerilog module for matrix multiplication
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Analytical modeling tool for CNNs running on array-based accelerators.
Visual representation of how systolic arrays made in Unity3d. (Just code)
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