verilog
Here are 3,811 public repositories matching this topic...
RISC-V Linux SoC, marchID: 0x2b
-
Updated
Jun 1, 2024 - AGS Script
XLS: Accelerated HW Synthesis
-
Updated
Jun 1, 2024 - C++
learn the combinational and sequential logic circuit.
-
Updated
Jun 1, 2024 - SystemVerilog
Verilator open-source SystemVerilog simulator and lint system
-
Updated
Jun 1, 2024 - C++
SystemVerilog compiler and language services
-
Updated
May 31, 2024 - C++
Veryl: A Modern Hardware Description Language
-
Updated
May 31, 2024 - Rust
Haskell to VHDL/Verilog/SystemVerilog compiler
-
Updated
May 31, 2024 - Haskell
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
-
Updated
Jun 1, 2024 - Verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
-
Updated
May 31, 2024 - Verilog
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
-
Updated
May 31, 2024 - JavaScript
RISC-V rv32i implementation on Tang Nano 9K
-
Updated
May 31, 2024 - Verilog
TT07 resub of tt04-raybox-zero "3D" VGA ray caster demo (like Wolf3D)
-
Updated
May 31, 2024 - Verilog
Improve this page
Add a description, image, and links to the verilog topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the verilog topic, visit your repo's landing page and select "manage topics."