rtl
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Veryl: A Modern Hardware Description Language
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Jun 6, 2024 - Rust
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Jun 6, 2024 - Verilog
hardware library for hwt (= ipcore repo)
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Jun 6, 2024 - Python
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Jun 6, 2024 - C
A Chisel RTL generator for network-on-chip interconnects
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Jun 6, 2024 - Scala
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
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Jun 6, 2024 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jun 6, 2024 - Verilog
VeeR EL2 Core
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Jun 6, 2024 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Jun 6, 2024 - SystemVerilog
A flexible and scalable development platform for modern FPGA projects.
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Jun 6, 2024 - Python
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
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Jun 6, 2024 - Verilog
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Jun 6, 2024 - JavaScript
Verilator open-source SystemVerilog simulator and lint system
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Jun 6, 2024 - C++
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Jun 6, 2024 - Scala
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