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Fusing macro argument eats up whitespace #5061

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tudortimi opened this issue Apr 21, 2024 · 5 comments
Open

Fusing macro argument eats up whitespace #5061

tudortimi opened this issue Apr 21, 2024 · 5 comments
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area: parser Issue involves SystemVerilog parsing status: ready Issue is ready for someone to fix; then goes to 'status: assigned'

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@tudortimi
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I have the following code:

class some_class;
endclass

`define some_macro(NAME) \
    class extension_for_``NAME`` extends some_class; \
    endclass \

`some_macro(foo)

I get the following error:

%Error: test.sv:8:37: syntax error, unexpected TYPE-IDENTIFIER, expecting ';'
    8 |     class  extension_for_fooextends some_class; 
      |                   

You can see that Verilator is not leaving a between foo and extends.

I'm using Verilator 5.024 and running with verilator test.sv --binary.

@tudortimi tudortimi added the new New issue not seen by maintainers label Apr 21, 2024
@wsnyder wsnyder added area: parser Issue involves SystemVerilog parsing status: ready Issue is ready for someone to fix; then goes to 'status: assigned' and removed new New issue not seen by maintainers labels Apr 22, 2024
@wsnyder
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wsnyder commented Apr 22, 2024

Surprising this was missed.

Might you be able to look at the V3PreProc code to see what's causing this and prepare a pull request? The t_preproc.v test should be updated to have this case in it.

@tudortimi
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This sounds like it would be simple enough. Sure, assign it to me.

@tudortimi tudortimi changed the title Fusing macro argument easts up whitespace Fusing macro argument eats up whitespace Apr 29, 2024
@tudortimi
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I had a look at the LRM and the trailing `` aren't needed for fusing class_for_ and NAME. In this case, extension_for_``NAME would be enough.

I'm not really 100% sure what NAME`` something should produce in this case. The LRM states:

A `` delimits lexical tokens without introducing white space [...].

Is considered a lexical token? Should it simply expand to the value of NAME followed by something, as if simply defining NAME something? (Other tools seem to do this.)

@tudortimi
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Assuming we want to fuse like in the above post, like all the other tools do, I had a look at the code and think I kinda got it.

I have the following macro in the test:

`define with_space_before_suffix(f) f`` suffix_after_space
`with_space_before_suffix(arg)

I see the preprocessor recognizing the arg`` part:

image
image

After arg gets put onto the stack and the state is set to JOIN, it hits the whitespace:

image
image

This line causes the space to be emitted and keeps the state as JOIN. (I'm guessing it then somehow jumps into the GETFETC part, which takes care of outputting the space, but didn't really follow how it gets there.) This explains why the expansion starts with arg (with space) and not arg (no space).

The next token is suffix_after_space, which also gets pushed to the stack as the RHS of the JOIN (the state left over):

image

This is because it still thinks it's in the JOIN that the should have actually ended.

I don't really know what code is needed to fix this, but I'm guessing there's some extra case needed to handle WHITE when in JOIN here:

image

@wsnyder
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wsnyder commented Apr 30, 2024

Your analysis seems correct, including likely some new text is needed to handle WHITE when in JOIN in your post above.

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Labels
area: parser Issue involves SystemVerilog parsing status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
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