What is the status for compilation for Xilinx FPGAs?

[jon-chuang]

How much work is required to set up development on Xilinx FPGAs? What is the status of the project vis-a-vis Intel's Clang SYCL? Is there a chance of Intel's SYCL compiling to Xilinx FPGAs? What is the compatibility of SPIR-V with Xilinx FPGAs?

From what I understand the triSYCL team has moved their work permanently to Intel's SYCL?

[j-stephan]

How much work is required to set up development on Xilinx FPGAs?

There are setup instructions somewhere in the triSYCL/sycl repository. If you want to use SYCL on Xilinx FPGAs you should use that project: github.com/triSYCL/sycl

From the top of my head:

1. Install SDAccel (or Vitis, as it is now called.)
2. Compile the Xilinx OpenCL runtime (github.com/Xilinx/XRT) using the master branch or the branch matching your version of SDAccel / Vitis. Depending on your distribution this might be a bit tricky. XRT's development focus seem to be Red Hat based distros (minus Fedora) whereas the SYCL compiler requires a more modern software environment (say Ubuntu 19.10).
3. If the above worked for you, download and install the environment and development shells for your accelerator from the Xilinx website.
4. Checkout the SYCL compiler project mentioned above, adjust your environment variables to point to your new SDAccel installation and compile everything. Once succeeded you should be able to compile the accompanying SYCL test suite.

What is the status of the project vis-a-vis Intel's Clang SYCL?

The compiler project mentioned above (which I will call Xilinx implementation from now on) is a direct fork of Intel's SYCL. In principle they are the same but the Xilinx implementation will lag behind a couple of weeks to months until the upstream changes are merged.

Is there a chance of Intel's SYCL compiling to Xilinx FPGAs?

IIRC this is not possible right now. The Xilinx implementation will give you a slightly older Intel SYCL + Xilinx FPGA targets, though.

What is the compatibility of SPIR-V with Xilinx FPGAs?

There is none I believe (the others might correct me on this). The Xilinx tools use a SPIR dialect called spir-df (for 'de facto') which differs from either SPIR or SPIR-V in certain aspects.

From what I understand the triSYCL team has moved their work permanently to Intel's SYCL?

Unless I am mistaken they are not working on Intel's implementation but on the fork. The original triSYCL is still alive and kicking since it follows a different purpose (being an environment for the SYCL committee to play around and experiment).

[keryell]

@j-stephan thank you for the clarification.

The main problem for us is that Vitis is still based on an old version of Clang/LLVM which renders things quite difficult. I should have more resource to work on SYCL for FPGA in 2 months to merge from up-stream Intel SYCL and experiment with the latest version of Vitis.
But it will remain very hackish until all the Xilinx toolchain move to the latest Clang/LLVM and remain synchronized with it.

[jon-chuang]

@keryell Two months is somewhat too long for me. You are saying that SDx works? Perhaps I need to get an SDx license for now.

[keryell]

Yes this is long, but keep in mind that anyway this is a research project that might work sometimes and has nothing in common with a supported product. :-) And in 2 months from now it will be the same... Just that it might use a more modern version of the Intel SYCL compiler with a more modern version of Xilinx Vitis.

[jon-chuang]

I'll try to see what works. And yes, actually, thanks for the hard work, this is an awesome project.

I wish Xilinx would give more official support now that Intel is doing so.

[keryell]

There is a new article describing the project: https://hgpu.org/?p=24496