The ISE Design Suite: Embedded Edition includes Xilinx Platform Studio (XPS), Software Development Kit (SDK), large repository of plug and play IP including MicroBlaze™ Soft Processor and peripherals, and a complete RTL to bit stream design flow. Embedded Edition provides the fundamental tools, technologies and familiar design flow to achieve op…

EC302-VLSI-Design-Lab

BRACU CSE460: VLSI Design Lab, Fall- 2021

Layout Description Framework, a framework to help semi-custom or full-custom designers create the layout of their ICs by writing C# code.

Solution for 2022 ICCAD Problem D: Wirelength Driven Detailed Macro Placemet

A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

EC804 Digital VLSI Testing and Testability Assignments.

vlsi lab experiments

This is a RISC-like implementation for a 5-stages pipelined processor implemented with Verilog which follows Harvard architecture with 2 separated memories one for the data and the other for the instructions.

In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.

A docker container with all of the tools needed for tapeout

Statistics Acquisition Module on Verilog

Gatery coding challenge: Implement PWM

Coursework of NTHU CS512200 VLSI Design for Manufacturability

design and verification of asynchronous circuits

This was my minor project in B.Tech ECE

Serial In Serial Out (SISO) shift registers are a kind of shift registers where both data loading as well as data retrieval to/from the shift register occurs in serial-mode. ... Initially all the flip-flops in the register are cleared by applying high on their clear pins. Next the input data word is fed serially to FF1.

东南大学计算机学院《VLSI系统导论》课程实验

This repository holds the VHDL codes and Verilog codes of the course named VLSI.