A High-performance Timing Analysis Tool for VLSI Systems
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Updated
May 26, 2023 - Verilog
A High-performance Timing Analysis Tool for VLSI Systems
Standard Cell Library based Memory Compiler using FF/Latch cells
A Standalone Structural Verilog Parser
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Library of approximate arithmetic circuits
VLSI EDA Global Router
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
genetic algorithm usage for routing optimization ( pyqt )
All the projects and assignments done as part of VLSI course.
This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect trad…
A generic object oriented library for solving optimizations problems with heuristic approaches + second-phase Genetic algorithm optimizations
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
FuzzyIWO-Algorithm (Adaptive fuzzy optimisation algorithm)
VLSI sketches & Arduino Code for the Android-controlled Multiple Hazard Detection, Path Retracing, and Rescue Robot, or AMRBot.
Graduate Level - Fundamental design issues involved in building reliable, safety-critical, and highly available systems. Topics include testing and fault-tolerant design of VLSI circuits, hardware and software fault tolerance, information redundancy, and fault-tolerant distributed systems.
VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic
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