vivado
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ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.
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Mar 11, 2023 - Verilog
Logic Analyzer IP Core
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Jul 23, 2022 - SystemVerilog
Custom VHDL to display the value on 4 LEDs on the board depending on the Pmod ENC encoder
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May 24, 2024 - Tcl
Display of various animated digital and analog clock using VGA control in FPGA
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May 23, 2018 - Verilog
Library containing various VHDL IPs
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Jan 5, 2024 - SystemVerilog
MultiCycle and Pipelined Processor designed for the course Computer Organisation of TUC
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Jun 5, 2022 - VHDL
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