verilator
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Algumas anotações de quem está aprendendo a sintetizar seu próprio microcontrolador em FPGA.
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May 6, 2021
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
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Apr 11, 2024 - Verilog
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
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May 4, 2024 - SystemVerilog
My notes and impement on Nand2Tetris courses
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Aug 29, 2022 - Assembly
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
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Sep 15, 2022 - SystemVerilog
FPGA based GPU for rendering ray marched scenes.
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May 17, 2024 - Verilog
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
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Aug 2, 2023 - Makefile
System Level Simulation and ASIC hardening flow for various designs using Systemverilog, Verilator and OpenROAD
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May 29, 2024 - Verilog
Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh,vscode 等开源工具链的开发环境。
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Jan 7, 2024 - Dockerfile
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