Script de PowerShell para configurar rápidamente un entorno de desarrollo SystemVerilog, incluyendo la instalación de VS Code, extensiones relevantes y herramientas de compilación
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Updated
Feb 20, 2024 - PowerShell
Script de PowerShell para configurar rápidamente un entorno de desarrollo SystemVerilog, incluyendo la instalación de VS Code, extensiones relevantes y herramientas de compilación
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
MIPS fine-grained multithreaded, five-stage pipelined, and software-interlocked core in SystemVerilog.
Course projects, capstone and individual studies.
Restricted Instruction Set Computer (V5) OTTER architecture for Xilinx Basys3 Board. Developed using Xilinx Vivado Suite
Demo of a simple 2 layer feed forward perceptron using system verilog (RISC V project)
Simple ipod made using System Verilog and implemented on the De1Soc
Educational project which goal is realization of processor with RISC-V architecture.
🖥️ Digital Design and Computer Architecture
Implementations of single-cycle & pipelined processors, experiments related to cache memory and more
This Repo contains some of my Verilog & SystemVerilog Programs.
SystemVerlilog-Projects
My Freshman & Junior year CS223, digital design, labs
An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.
Exercícios desenvolvidos durante a disciplina Concepção Estruturada de Circuitos Integrados, relacionando os mais diversos assuntos da mesma.
First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.
Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh,vscode 等开源工具链的开发环境。
Quartus II Pipelined Processor
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