OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
May 28, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
A textbook on system on chip design using Arm Cortex-A
BDD Gherkin implementation in native SystemVerilog, based on UVM.
A reference book on System-on-Chip Design
Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.
SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course
Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages
A textbook on understanding system on chip design
ECE2300: Digital Logic and Computer Organization
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