OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
May 28, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Fully-differential asynchronous non-binary 12-bit SAR-ADC
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
Standard cells for SKY90FD provided by SkyWater.
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
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